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[core] code format

This commit is contained in:
tangxifan 2024-08-02 14:23:35 -07:00
parent f7e30b9974
commit f44c45bdd3
2 changed files with 9 additions and 12 deletions
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18
openfpga/src/base/openfpga_pb_pin_fixup.cpp
View File

@ -36,8 +36,7 @@ static void update_cluster_pin_with_post_routing_results(
const VprRoutingAnnotation& vpr_routing_annotation, const VprRoutingAnnotation& vpr_routing_annotation,
VprClusteringAnnotation& vpr_clustering_annotation, const size_t& layer, VprClusteringAnnotation& vpr_clustering_annotation, const size_t& layer,
const vtr::Point<size_t>& grid_coord, const ClusterBlockId& blk_id, const vtr::Point<size_t>& grid_coord, const ClusterBlockId& blk_id,
const e_side& border_side, const size_t& z, const e_side& border_side, const size_t& z, const bool& perimeter_cb,
const bool& perimeter_cb,
const bool& verbose) { const bool& verbose) {
/* Handle each pin */ /* Handle each pin */
auto logical_block = clustering_ctx.clb_nlist.block_type(blk_id); auto logical_block = clustering_ctx.clb_nlist.block_type(blk_id);
@ -79,10 +78,10 @@ static void update_cluster_pin_with_post_routing_results(
VTR_ASSERT(1 == pin_sides.size()); VTR_ASSERT(1 == pin_sides.size());
pin_side = pin_sides[0]; pin_side = pin_sides[0];
} else if (perimeter_cb) { } else if (perimeter_cb) {
/* When perimeter connection blcoks are allowed, I/O pins may occur on any side but the border side */ /* When perimeter connection blcoks are allowed, I/O pins may occur on any
VTR_ASSERT(pin_sides.end() != std::find(pin_sides.begin(), * side but the border side */
pin_sides.end(), VTR_ASSERT(pin_sides.end() !=
border_side)); std::find(pin_sides.begin(), pin_sides.end(), border_side));
VTR_ASSERT(1 == pin_sides.size()); VTR_ASSERT(1 == pin_sides.size());
pin_side = pin_sides[0]; pin_side = pin_sides[0];
} else { } else {
@ -197,8 +196,7 @@ void update_pb_pin_with_post_routing_results(
const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx, const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx,
const PlacementContext& placement_ctx, const PlacementContext& placement_ctx,
const VprRoutingAnnotation& vpr_routing_annotation, const VprRoutingAnnotation& vpr_routing_annotation,
VprClusteringAnnotation& vpr_clustering_annotation, VprClusteringAnnotation& vpr_clustering_annotation, const bool& perimeter_cb,
const bool& perimeter_cb,
const bool& verbose) { const bool& verbose) {
/* Ensure a clean start: remove all the remapping results from VTR's /* Ensure a clean start: remove all the remapping results from VTR's
* post-routing clustering result sync-up */ * post-routing clustering result sync-up */
@ -261,8 +259,8 @@ void update_pb_pin_with_post_routing_results(
update_cluster_pin_with_post_routing_results( update_cluster_pin_with_post_routing_results(
device_ctx, clustering_ctx, vpr_routing_annotation, device_ctx, clustering_ctx, vpr_routing_annotation,
vpr_clustering_annotation, layer, io_coord, cluster_blk_id, io_side, vpr_clustering_annotation, layer, io_coord, cluster_blk_id, io_side,
placement_ctx.block_locs[cluster_blk_id].loc.sub_tile, placement_ctx.block_locs[cluster_blk_id].loc.sub_tile, perimeter_cb,
perimeter_cb, verbose); verbose);
} }
} }
} }

3
openfpga/src/base/openfpga_pb_pin_fixup.h
View File

@ -18,8 +18,7 @@ void update_pb_pin_with_post_routing_results(
const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx, const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx,
const PlacementContext& placement_ctx, const PlacementContext& placement_ctx,
const VprRoutingAnnotation& vpr_routing_annotation, const VprRoutingAnnotation& vpr_routing_annotation,
VprClusteringAnnotation& vpr_clustering_annotation, VprClusteringAnnotation& vpr_clustering_annotation, const bool& perimeter_cb,
const bool& perimeter_cb,
const bool& verbose); const bool& verbose);
} /* end namespace openfpga */ } /* end namespace openfpga */