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[Script] Add route chan width option to vtr openfpga script

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tangxifan 2021-03-20 22:00:09 -06:00
parent 9a3aff274f
commit eca2a35612
1 changed files with 1 additions and 1 deletions
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openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga
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@ -2,7 +2,7 @@
# When the global clock is defined as a port of a tile, clock routing in VPR should be skipped # When the global clock is defined as a port of a tile, clock routing in VPR should be skipped
# This is due to the Fc_in of clock port is set to 0 for global wiring # This is due to the Fc_in of clock port is set to 0 for global wiring
#--write_rr_graph example_rr_graph.xml #--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH}
# Read OpenFPGA architecture definition # Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}