From eca2a35612adc60ab19bf2c24479f477fe71e8ac Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 20 Mar 2021 22:00:09 -0600 Subject: [PATCH] [Script] Add route chan width option to vtr openfpga script --- .../vtr_benchmark_example_script.openfpga | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga index 01e1c6bf0..fdf0f7146 100644 --- a/openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga @@ -2,7 +2,7 @@ # When the global clock is defined as a port of a tile, clock routing in VPR should be skipped # This is due to the Fc_in of clock port is set to 0 for global wiring #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}