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add default configurable memory model set-up when reading openfpga architecture XML

This commit is contained in:
tangxifan 2020-02-12 15:19:40 -07:00
parent c78d3e9af1
commit df3ae60954
3 changed files with 57 additions and 0 deletions
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47
libopenfpga/libarchopenfpga/src/openfpga_arch_linker.cpp
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@ -3,6 +3,8 @@
* data structures inside the openfpga arch data structure
*******************************************************************/
#include "vtr_log.h"
#include "vtr_assert.h"
#include "openfpga_arch_linker.h"
/********************************************************************
@ -21,3 +23,48 @@ void link_config_protocol_to_circuit_library(openfpga::Arch& openfpga_arch) {
openfpga_arch.config_protocol.set_memory_model(config_memory_model);
}
/********************************************************************
* Link the circuit model of SRAM ports of each circuit model
* to a default SRAM circuit model.
* This function aims to ease the XML writing, allowing users to skip
* the circuit model definition for SRAM ports that are used by default
* TODO: Maybe deprecated as we prefer strict definition
*******************************************************************/
void config_circuit_models_sram_port_to_default_sram_model(CircuitLibrary& circuit_lib,
const CircuitModelId& default_sram_model) {
VTR_ASSERT(CircuitModelId::INVALID() != default_sram_model);
for (const auto& model : circuit_lib.models()) {
for (const auto& port : circuit_lib.model_ports(model)) {
/* Bypass non SRAM ports */
if (CIRCUIT_MODEL_PORT_SRAM != circuit_lib.port_type(port)) {
continue;
}
/* Write for the default SRAM SPICE model! */
circuit_lib.set_port_tri_state_model_id(port, default_sram_model);
/* Only show warning when we try to override the given spice_model_name ! */
if (true == circuit_lib.port_tri_state_model_name(port).empty()) {
VTR_LOG("Use the default configurable memory model '%s' for circuit model '%s' port '%s')\n",
circuit_lib.model_name(default_sram_model).c_str(),
circuit_lib.model_name(model).c_str(),
circuit_lib.port_prefix(port).c_str());
continue;
}
/* Give a warning !!! */
if (circuit_lib.model_name(default_sram_model) != circuit_lib.port_tri_state_model_name(port)) {
VTR_LOG_WARN("Overwrite SRAM circuit model for circuit model port (name:%s, port:%s) to be the correct one (name:%s)!\n",
circuit_lib.model_name(model).c_str(),
circuit_lib.port_prefix(port).c_str(),
circuit_lib.model_name(default_sram_model).c_str());
}
}
}
/* Rebuild the submodels for circuit_library
* because we have created links for ports
*/
circuit_lib.build_model_links();
}

3
libopenfpga/libarchopenfpga/src/openfpga_arch_linker.h
View File

@ -5,4 +5,7 @@
void link_config_protocol_to_circuit_library(openfpga::Arch& openfpga_arch);
void config_circuit_models_sram_port_to_default_sram_model(CircuitLibrary& circuit_lib,
const CircuitModelId& default_sram_model);
#endif

7
libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp
View File

@ -70,6 +70,13 @@ openfpga::Arch read_xml_openfpga_arch(const char* arch_file_name) {
/* Build the internal link between configuration protocol and circuit library */
link_config_protocol_to_circuit_library(openfpga_arch);
/* Now, we can know the default configurable memory model
* Apply it to all the SRAM ports of circuit models
*/
config_circuit_models_sram_port_to_default_sram_model(openfpga_arch.circuit_lib,
openfpga_arch.config_protocol.memory_model());
/* Parse the connection block circuit definition */
openfpga_arch.cb_switch2circuit = read_xml_cb_switch_circuit(xml_openfpga_arch, loc_data,
openfpga_arch.circuit_lib);