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Merge pull request #143 from lnis-uofu/dev 

Critical Bug fix in the XML Syntax when Defining Default Values for A Global Tile Port
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tangxifan 2020-12-02 18:41:25 -07:00 committed by GitHub
parent 621f989c9b 412fb5bb31
commit d71f0537bc
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3 changed files with 5 additions and 3 deletions
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4
docs/source/manual/arch_lang/annotate_vpr_arch.rst
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@ -60,7 +60,7 @@ Here is an example:
.. code-block:: xml
<tile_annotations>
<global_port name="<string>" tile_port="<string>" is_clock="<bool>" is_reset="<bool>" is_set="<bool>"/>
<global_port name="<string>" tile_port="<string>" is_clock="<bool>" is_reset="<bool>" is_set="<bool>" default_val="<int>"/>
</tile_annotations>
- ``name="<string>"`` is the port name to appear in the top-level FPGA fabric.
@ -85,6 +85,8 @@ Here is an example:
.. note:: All the global port from a physical tile port is only used in operating phase. Any ports for programmable use are not allowed!
- ``default_val="<int>"`` define if the default value for the global port when initialized in testbenches. Valid values are either ``0`` or ``1``. For example, the default value of an active-high reset pin is ``0``, while an active-low reset pin is ``1``.
A more illustrative example:
:numref:`fig_global_tile_ports` illustrates the difference between the global ports defined through ``circuit_model`` and ``tile_annotation``.

2
libopenfpga/libarchopenfpga/src/read_xml_tile_annotation.cpp
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@ -67,7 +67,7 @@ void read_xml_tile_global_port_annotation(pugi::xml_node& xml_tile,
tile_annotation.set_global_port_is_reset(tile_global_port_id, get_attribute(xml_tile, "is_reset", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
/* Get default_value attributes */
tile_annotation.set_global_port_default_value(tile_global_port_id, get_attribute(xml_tile, "default_value", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(0));
tile_annotation.set_global_port_default_value(tile_global_port_id, get_attribute(xml_tile, "default_val", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(0));
/* Ensure valid port attributes */
if (false == tile_annotation.valid_global_port_attributes(tile_global_port_id)) {

2
openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
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@ -218,7 +218,7 @@
</direct_connection>
<tile_annotations>
<global_port name="clk" tile_port="clb.clk" is_clock="true" default_val="0"/>
<global_port name="reset" tile_port="clb.reset" is_reset="true" default_val="1"/>
<global_port name="reset" tile_port="clb.reset" is_reset="true" default_val="0"/>
</tile_annotations>
<pb_type_annotations>
<!-- physical pb_type binding in complex block IO -->