From d195b9e32c343ed24b54e257d7f03e52b51997b1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 2 Dec 2020 17:03:48 -0700 Subject: [PATCH 1/3] [Tool] Bug fix in XML syntax to define default values for a global tile port --- libopenfpga/libarchopenfpga/src/read_xml_tile_annotation.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libopenfpga/libarchopenfpga/src/read_xml_tile_annotation.cpp b/libopenfpga/libarchopenfpga/src/read_xml_tile_annotation.cpp index 692cd2288..28d2a6ab8 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_tile_annotation.cpp +++ b/libopenfpga/libarchopenfpga/src/read_xml_tile_annotation.cpp @@ -67,7 +67,7 @@ void read_xml_tile_global_port_annotation(pugi::xml_node& xml_tile, tile_annotation.set_global_port_is_reset(tile_global_port_id, get_attribute(xml_tile, "is_reset", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false)); /* Get default_value attributes */ - tile_annotation.set_global_port_default_value(tile_global_port_id, get_attribute(xml_tile, "default_value", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(0)); + tile_annotation.set_global_port_default_value(tile_global_port_id, get_attribute(xml_tile, "default_val", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(0)); /* Ensure valid port attributes */ if (false == tile_annotation.valid_global_port_attributes(tile_global_port_id)) { From 8350b0f911d010f969d28cbd4cc25db32d9c2c19 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 2 Dec 2020 17:08:34 -0700 Subject: [PATCH 2/3] [Doc] Update documentation about default value definition in tile annotation --- docs/source/manual/arch_lang/annotate_vpr_arch.rst | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/docs/source/manual/arch_lang/annotate_vpr_arch.rst b/docs/source/manual/arch_lang/annotate_vpr_arch.rst index 8a1a53d70..b5d8a93e5 100644 --- a/docs/source/manual/arch_lang/annotate_vpr_arch.rst +++ b/docs/source/manual/arch_lang/annotate_vpr_arch.rst @@ -60,7 +60,7 @@ Here is an example: .. code-block:: xml - + - ``name=""`` is the port name to appear in the top-level FPGA fabric. @@ -85,6 +85,8 @@ Here is an example: .. note:: All the global port from a physical tile port is only used in operating phase. Any ports for programmable use are not allowed! +- ``default_val=""`` define if the default value for the global port when initialized in testbenches. Valid values are either ``0`` or ``1``. For example, the default value of an active-high reset pin is ``0``, while an active-low reset pin is ``1``. + A more illustrative example: :numref:`fig_global_tile_ports` illustrates the difference between the global ports defined through ``circuit_model`` and ``tile_annotation``. From 412fb5bb317273db12db85b84d15b8a3fe1beafa Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 2 Dec 2020 17:51:50 -0700 Subject: [PATCH 3/3] [Arch] Bug fix due to valid default value parser --- ...ter_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index c543b9fa7..0ad0bd1a6 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -218,7 +218,7 @@ - +