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tutorials/fpga_flow/folder_organization.md

@@ -0,0 +1,23 @@
+# fpga_flow folder organization
+
+The fpga_flow folder is organized as follow:
+* [**arch**]: contains architectures description files
+* [**benchmarks**]: contains Verilog and blif benchmarks + lists
+* [**configs**]: contains configuration files to run fpga_flow.pl
+* [**scripts**]: contains all the scripts required to run the flow
+* [**tech**]: contains xml tech files for power estimation
+
+## arch
+In this folder are saved the architecture files. These files are Hardware description for the FPGA written in XML. This folder contains 3 sub-folders:
+- **fpga_spice**: contains existing architecture ready to use.
+- **template**: contains template architecture which contain keyword to replace
+- **generated**: empty at the beginning, will host rewritten template
+
+## benchmarks
+This folder contains benchmarks to implement in the FPGA.
+
+## configs
+
+## scripts
+
+## tech

tutorials/fpga_flow/how2use.md

@@ -1,7 +1,7 @@
 # FPGA flow
 
 This tutorial will help the user to understand how to use OpenFPGA flow.<br />
-During this tutorial we consider the user start in the OpenFPGA folder and we'll use tips and informations provided in [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/tutorial_index.md#tips-and-informations).
+During this tutorial we consider the user start in the OpenFPGA folder and we'll use tips and informations provided in [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/tutorial_index.md#tips-and-informations). Details on how the folder is organized are available [here](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/folder_organization.md).
 
 ## Running fpga_flow.pl
 
@@ -16,29 +16,9 @@ cd fpga_flow<br />
 
 By running this script we took an architecture description file, generated its netlist, generated a bitstream to implement a benchmark on it and verified this implementation.<br />
 When you open this file you can see that 2 scripts are called. The first one is **rewrite_path_in_file.pl** which allow us to make this tutorial generic by generating full path to dependancies.<br />
-The second one is **fpga_flow.pl**. This script launch OpenFPGA flow andcan be used with a lot of [options](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/options.md)
+The second one is **fpga_flow.pl**. This script launch OpenFPGA flow and can be used with a lot of [options](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/options.md). In this example we activated all FPGA-Verilog options
 
-Once the configuration is done, we can select which option we want to enable in fpga_flow. fpga_flow options don't exactly have the name of those listed in the [documentation](https://openfpga.readthedocs.io/en/master/fpga_verilog/command_line_usage.html "documentation"), which are used on the modifed version of vpr. Indeed, where vpr will take an option as "**--fpga_XXX**" fpgs_flow will call it "**-vpr_fpga_XXX**".<br />
-Few options are only in fpga_flow:
-* **-N**: number of LUT per CLB
-* **-K**: LUT size/ number of input
-* **-rpt <path>**: specifies wherever fpga_flow will write its report
-* **-ace_d <int_value>**: specifies inputs average probability of switching
-* **-multi_thread <int_value>**: specifies number of core to use
-* **-end_flow_with_test**: uses Icarus Verilog to verify generated netlist
 
-**
-
-The folder is organized as follow:
-* **arch**: contains architectures description files
-* **benchmarks**: contains Verilog and blif benchmarks + lists
-* **configs**: contains configuration files to run fpga_flow.pl
-* **scripts**: contains all the scripts required to run the flow
-* **tech**: contains xml tech files for power estimation
-
-fpga_flow.pl is saved in OPENFPGAPATHKEYWORD/fpga_flow/scripts. If we look in this folder, we can find some other scripts as:
-* pro_blif.pl: rewrite a blif which has only 3 members in a .latch module
-* rewrite_path_in_file.pl: target a keyword in a file and replace it
 
 *Any script provides help if launch without argument*
 

tutorials/fpga_flow/options.md

@@ -21,6 +21,7 @@ Mandatory options: <br />
 - -parse_results_only : *only parse the flow results and write CSV report.*
 - -debug : *debug mode*
 - -help : *print usage*
+- -end_flow_with_test: *Uses Icarus Verilog simulator to verified bencmark implementation*
 ### ODIN II
 - -min_hard_adder_size: *min. size of hard adder in carry chain defined in Arch XML.(Default:1)*
 - -mem_size: *size of memory, mandatory when VTR/VTR_MCCL/VTR_MIG_MCCL flow is chosen*
@@ -55,11 +56,11 @@ Mandatory options: <br />
 - -vpr_fpga_spice_testbench_load_extraction_off : *turn off testbench_load_extraction in VPR FPGA SPICE*
 - -vpr_fpga_spice_simulator_path <string> : *Specify simulator path*
 ### VPR - FPGA-Verilog Extension
-- -vpr_fpga_verilog : *turn on Verilog Generator of VPR FPGA SPICE*
+- -vpr_fpga_verilog : *turn on OpenFPGA Verilog Generator*
 - -vpr_fpga_verilog_dir <verilog_path>: *provides the path where generated verilog files will be written*
 - -vpr_fpga_verilog_include_timing : *turn on printing delay specification in Verilog files*
 - -vpr_fpga_verilog_include_signal_init : *turn on printing signal initialization in Verilog files*
-- -vpr_fpga_verilog_print_autocheck_top_testbench: *turn on printing autochecked top-level testbench for Verilog Generator of VPR FPGA SPICE*
+- -vpr_fpga_verilog_print_autocheck_top_testbench: *turn on printing autochecked top-level testbench for OpenFPGA Verilog Generator*
 - -vpr_fpga_verilog_formal_verification_top_netlist : *turn on printing formal top Verilog files*
 - -vpr_fpga_verilog_include_icarus_simulator : *Add syntax and definition required to use Icarus Verilog simulator*
 - -vpr_fpga_verilog_print_user_defined_template : *Generates a template of hierarchy modules and their port mapping*
@@ -67,8 +68,8 @@ Mandatory options: <br />
 - -vpr_fpga_verilog_report_timing_rpt_path <path_to_generate_reports> : *Specify path for report timing*
 - -vpr_fpga_verilog_print_sdc_pnr : *Generates sdc file to constraint Hardware P&R*
 - -vpr_fpga_verilog_print_sdc_analysis : *Generates sdc file to do STA*
-- -vpr_fpga_verilog_print_top_tb : *turn on printing top-level testbench for Verilog Generator of VPR FPGA SPICE*
-- -vpr_fpga_verilog_print_input_blif_tb : *turn on printing testbench for input blif file in Verilog Generator of VPR FPGA SPICE*
+- -vpr_fpga_verilog_print_top_tb : *turn on printing top-level testbench for OpenFPGA Verilog Generator*
+- -vpr_fpga_verilog_print_input_blif_tb : *turn on printing testbench for input blif file in OpenFPGA Verilog Generator*
 - -vpr_fpga_verilog_print_modelsim_autodeck <modelsim.ini_path>: *turn on printing modelsim simulation script*
 ### VPR - FPGA-Bitstream Extension
 - -vpr_fpga_bitstream_generator: *turn on FPGA-SPICE bitstream generator*