riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Hot fix

This commit is contained in:
Baudouin Chauviere 2019-07-11 17:39:02 -06:00
parent d0cd5a2bc1
commit c9b84f61c9
1 changed files with 6 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
View File

@ -373,7 +373,9 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp,
fprintf(fp, ".%s(",
pb_type_port->spice_model_port->lib_name);
}
fprintf(fp, "{");
if (1 < pb_type_port_num_pins) {
fprintf(fp, "{");
}
for (int ipin = 0; ipin < pb_type_port->num_pins; ++ipin) {
if (0 < ipin) {
fprintf(fp, ", ");
@ -381,7 +383,9 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp,
fprintf(fp, "%s",
gen_verilog_one_pb_type_pin_name(port_prefix, pb_type_port, ipin));
}
fprintf(fp, "}");
if (1 < pb_type_port_num_pins) {
fprintf(fp, "}");
}
if (TRUE == dump_explicit_port_map) {
fprintf(fp, ")");
}