From c9b84f61c94fdb82997d0ddccc9702677e9ff371 Mon Sep 17 00:00:00 2001
From: Baudouin Chauviere <baudouin.chauviere@utah.edu>
Date: Thu, 11 Jul 2019 17:39:02 -0600
Subject: [PATCH] Hot fix

---
 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
index 25c162c48..b65b652d5 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
@@ -373,7 +373,9 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp,
       fprintf(fp, ".%s(", 
               pb_type_port->spice_model_port->lib_name);
     }
-    fprintf(fp, "{"); 
+    if (1 < pb_type_port_num_pins) {
+      fprintf(fp, "{"); 
+    }
     for (int ipin = 0; ipin < pb_type_port->num_pins; ++ipin) {
       if (0 < ipin) {
         fprintf(fp, ", "); 
@@ -381,7 +383,9 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp,
       fprintf(fp, "%s", 
               gen_verilog_one_pb_type_pin_name(port_prefix, pb_type_port, ipin));
     }
-    fprintf(fp, "}"); 
+    if (1 < pb_type_port_num_pins) {
+      fprintf(fp, "}"); 
+    }
     if (TRUE == dump_explicit_port_map) {
       fprintf(fp, ")");
     }