Merge branch 'tileable_routing' into dev
This commit is contained in:
commit
c6a4d29ed8
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@ -1324,6 +1324,10 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir,
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clock_t t_end;
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clock_t t_end;
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float run_time_sec;
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float run_time_sec;
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clock_t t_start_profiling;
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clock_t t_end_profiling;
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float run_time_sec_profiling = 0.;
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/* Start time count */
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/* Start time count */
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t_start = clock();
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t_start = clock();
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@ -1342,8 +1346,15 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir,
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LL_num_rr_nodes, LL_rr_node,
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LL_num_rr_nodes, LL_rr_node,
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LL_rr_node_indices,
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LL_rr_node_indices,
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num_segments, LL_rr_indexed_data);
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num_segments, LL_rr_indexed_data);
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/* For profiling */
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t_start_profiling = clock();
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/* sort drive_rr_nodes */
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/* sort drive_rr_nodes */
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sort_rr_gsb_drive_rr_nodes(rr_gsb);
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sort_rr_gsb_drive_rr_nodes(rr_gsb);
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/* End time count */
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t_end_profiling = clock();
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run_time_sec_profiling += (float)(t_end_profiling - t_start_profiling) / CLOCKS_PER_SEC;
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/* Add to device_rr_gsb */
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/* Add to device_rr_gsb */
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DeviceCoordinator sb_coordinator = rr_gsb.get_sb_coordinator();
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DeviceCoordinator sb_coordinator = rr_gsb.get_sb_coordinator();
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LL_device_rr_gsb.add_rr_gsb(sb_coordinator, rr_gsb);
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LL_device_rr_gsb.add_rr_gsb(sb_coordinator, rr_gsb);
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@ -1360,6 +1371,8 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir,
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run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC;
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run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC;
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vpr_printf(TIO_MESSAGE_INFO, "Backannotation of Switch Block took %g seconds\n\n", run_time_sec);
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vpr_printf(TIO_MESSAGE_INFO, "Backannotation of Switch Block took %g seconds\n\n", run_time_sec);
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vpr_printf(TIO_MESSAGE_INFO, "Edge sorting for Switch Block took %g seconds\n\n", run_time_sec_profiling);
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if (TRUE == output_sb_xml) {
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if (TRUE == output_sb_xml) {
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create_dir_path(sb_xml_dir);
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create_dir_path(sb_xml_dir);
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@ -1019,7 +1019,7 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or
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/* Get X-channel CB coordinator */
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/* Get X-channel CB coordinator */
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const DeviceCoordinator cbx_coordinator = rr_gsb.get_cb_coordinator(CHANX);
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const DeviceCoordinator cbx_coordinator = rr_gsb.get_cb_coordinator(CHANX);
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/* X - channels [1...nx][0..ny]*/
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/* X - channels [1...nx][0..ny]*/
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if ((TRUE == is_cb_exist(CHANX, cbx_coordinator.get_x(), cbx_coordinator.get_x()))
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if ((TRUE == is_cb_exist(CHANX, cbx_coordinator.get_x(), cbx_coordinator.get_y()))
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&&(true == rr_gsb.is_cb_exist(CHANX))) {
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&&(true == rr_gsb.is_cb_exist(CHANX))) {
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dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANX, is_explicit_mapping);
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dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANX, is_explicit_mapping);
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}
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}
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@ -1027,7 +1027,7 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or
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/* Get X-channel CB coordinator */
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/* Get X-channel CB coordinator */
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const DeviceCoordinator cby_coordinator = rr_gsb.get_cb_coordinator(CHANY);
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const DeviceCoordinator cby_coordinator = rr_gsb.get_cb_coordinator(CHANY);
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/* Y - channels [1...ny][0..nx]*/
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/* Y - channels [1...ny][0..nx]*/
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if ((TRUE == is_cb_exist(CHANY, cby_coordinator.get_x(), cby_coordinator.get_x()))
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if ((TRUE == is_cb_exist(CHANY, cby_coordinator.get_x(), cby_coordinator.get_y()))
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&&(true == rr_gsb.is_cb_exist(CHANY))) {
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&&(true == rr_gsb.is_cb_exist(CHANY))) {
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dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANY, is_explicit_mapping);
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dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANY, is_explicit_mapping);
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}
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}
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