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[Test] Update bitstream annotation with new syntax

This commit is contained in:
tangxifan 2021-03-10 20:45:17 -07:00
parent 7d07f5d8cb
commit a6186db315
2 changed files with 2 additions and 2 deletions
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2
openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml
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@ -1,4 +1,4 @@
<openfpga_bitstream_setting>
<pb_type name="clb.fle[arithmetic].soft_adder.adder_lut4" source="eblif" content=".param LUT"/>
<pb_type name="clb.fle[arithmetic].soft_adder.adder_lut4" source="eblif" content=".param IN2_IS_CIN" overwrite_mode_bits="true" offset="0"/>
<pb_type name="clb.fle[arithmetic].soft_adder.adder_lut4" source="eblif" content=".param IN2_IS_CIN" is_mode_select_bitstream="true" bitstream_offset="0"/>
</openfpga_bitstream_setting>

2
openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf
View File

@ -31,7 +31,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/ad
[SYNTHESIS_PARAM]
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
bench1_top = adder_8