diff --git a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml
index 52e7347f2..b02afba78 100644
--- a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml
+++ b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml
@@ -1,4 +1,4 @@
 <openfpga_bitstream_setting>
   <pb_type name="clb.fle[arithmetic].soft_adder.adder_lut4" source="eblif" content=".param LUT"/>
-  <pb_type name="clb.fle[arithmetic].soft_adder.adder_lut4" source="eblif" content=".param IN2_IS_CIN" overwrite_mode_bits="true" offset="0"/>
+  <pb_type name="clb.fle[arithmetic].soft_adder.adder_lut4" source="eblif" content=".param IN2_IS_CIN" is_mode_select_bitstream="true" bitstream_offset="0"/>
 </openfpga_bitstream_setting>
diff --git a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf
index a82abfd59..8d8a16eb6 100644
--- a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf
+++ b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf
@@ -31,7 +31,7 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/ad
 
 [SYNTHESIS_PARAM]
 bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/qlf_yosys.ys
-bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys
+bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
 
 bench1_top = adder_8