riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Update link for _user_defined_template.v 

This ensures it goes to the correct page after pull request 274 no longer works
This commit is contained in:
bbleaptrot 2021-04-12 14:00:54 -06:00 committed by GitHub
parent f626b17d04
commit a2c2b634e6
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
docs/source/tutorials/arch_modeling/user_defined_temp_tutorial.rst
View File

@ -167,4 +167,4 @@ Finally, rerun this command from the OpenFPGA root directory to ensure it is wor
python3 openfpga_flow/scripts_run_fpga_task.py fpga_verilog/adder/hard_adder --debug --show_thread_logs
.. _user_defined_template.v: https://openfpga--274.org.readthedocs.build/en/274/manual/fpga_verilog/fabric_netlist/#cmdoption-arg-user_defined_templates.v
.. _user_defined_template.v: https://openfpga.readthedocs.io/en/master/manual/fpga_verilog/fabric_netlist/#cmdoption-arg-user_defined_templates.v