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bug fix for arch decoder Verilog codes. Now Modelsim compiles ok.

This commit is contained in:
tangxifan 2020-05-28 18:29:22 -06:00
parent 6a72c66eb8
commit 986956e474
1 changed files with 2 additions and 2 deletions
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4
openfpga/src/fpga_verilog/verilog_decoders.cpp
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@ -301,8 +301,8 @@ void print_verilog_arch_decoder_module(std::fstream& fp,
if (1 == data_size) {
fp << "always@(" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ") begin" << std::endl;
fp << "\tif (" << generate_verilog_port(VERILOG_PORT_CONKT, enable_port) << " == 1'b1) begin" << std::endl;
fp << "\t";
print_verilog_wire_connection(fp, data_port, addr_port, false);
fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, data_port);
fp << " = " << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ";" << std::endl;
fp << "\t" << "end" << std::endl;
fp << "end" << std::endl;