From 986956e47468c2213912a3886ed2879b69ac141e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 28 May 2020 18:29:22 -0600 Subject: [PATCH] bug fix for arch decoder Verilog codes. Now Modelsim compiles ok. --- openfpga/src/fpga_verilog/verilog_decoders.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_decoders.cpp b/openfpga/src/fpga_verilog/verilog_decoders.cpp index 70b65ee61..2637736ea 100644 --- a/openfpga/src/fpga_verilog/verilog_decoders.cpp +++ b/openfpga/src/fpga_verilog/verilog_decoders.cpp @@ -301,8 +301,8 @@ void print_verilog_arch_decoder_module(std::fstream& fp, if (1 == data_size) { fp << "always@(" << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ") begin" << std::endl; fp << "\tif (" << generate_verilog_port(VERILOG_PORT_CONKT, enable_port) << " == 1'b1) begin" << std::endl; - fp << "\t"; - print_verilog_wire_connection(fp, data_port, addr_port, false); + fp << "\t\t" << generate_verilog_port(VERILOG_PORT_CONKT, data_port); + fp << " = " << generate_verilog_port(VERILOG_PORT_CONKT, addr_port) << ";" << std::endl; fp << "\t" << "end" << std::endl; fp << "end" << std::endl;