adding dff synth
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Nachiket Kapre
parent
b14b5f975d
commit
95fe4d7dae
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@ -0,0 +1,360 @@
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//-----------------------------------------------------
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// Design Name : D-type Flip-flops
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// File Name : ff.v
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// Coder : Xifan TANG
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//-----------------------------------------------------
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//-----------------------------------------------------
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// Function : A native D-type flip-flop with single output
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//-----------------------------------------------------
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module DFFQ (
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input CK, // Clock Input
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input D, // Data Input
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output Q // Q output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ (posedge CK) begin
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q_reg <= D;
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end
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : A native D-type flip-flop
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//-----------------------------------------------------
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module DFF (
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input CK, // Clock Input
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input D, // Data Input
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output Q, // Q output
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output QN // QB output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ (posedge CK) begin
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q_reg <= D;
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end
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - single output
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// - asynchronous active high reset
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//-----------------------------------------------------
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module DFFRQ (
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input RST, // Reset input
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input CK, // Clock Input
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input D, // Data Input
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output Q // Q output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge CK or posedge RST)
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if (RST) begin
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q_reg <= 1'b0;
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end else begin
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q_reg <= D;
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end
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - asynchronous active high reset
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//-----------------------------------------------------
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module DFFR (
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input RST, // Reset input
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input CK, // Clock Input
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input D, // Data Input
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output Q, // Q output
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output QN // QB output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge CK or posedge RST)
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if (RST) begin
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q_reg <= 1'b0;
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end else begin
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q_reg <= D;
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end
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - asynchronous active low reset
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//-----------------------------------------------------
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module DFFRN (
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input RSTN, // Reset input
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input CK, // Clock Input
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input D, // Data Input
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output Q, // Q output
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output QN // QB output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge CK or negedge RSTN)
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if (~RSTN) begin
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q_reg <= 1'b0;
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end else begin
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q_reg <= D;
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end
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - asynchronous active high set
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//-----------------------------------------------------
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module DFFS (
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input SET, // Set input
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input CK, // Clock Input
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input D, // Data Input
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output Q, // Q output
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output QN // QB output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge CK or posedge SET)
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if (SET) begin
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q_reg <= 1'b1;
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end else begin
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q_reg <= D;
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end
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - asynchronous active low set
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//-----------------------------------------------------
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module DFFSN (
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input SETN, // Set input
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input CK, // Clock Input
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input D, // Data Input
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output Q, // Q output
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output QN // QB output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge CK or negedge SETN)
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if (~SETN) begin
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q_reg <= 1'b1;
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end else begin
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q_reg <= D;
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end
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - asynchronous active high reset
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// - asynchronous active high set
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//-----------------------------------------------------
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module DFFSR (
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input SET, // set input
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input RST, // Reset input
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input CK, // Clock Input
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input D, // Data Input
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output Q, // Q output
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output QN // QB output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge CK or posedge RST or posedge SET)
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if (RST) begin
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q_reg <= 1'b0;
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end else if (SET) begin
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q_reg <= 1'b1;
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end else begin
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q_reg <= D;
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end
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - asynchronous active high reset
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// - asynchronous active high set
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//-----------------------------------------------------
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module DFFSRQ (
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input SET, // set input
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input RST, // Reset input
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input CK, // Clock Input
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input D, // Data Input
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output Q // Q output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge CK or posedge RST or posedge SET)
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if (RST) begin
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q_reg <= 1'b0;
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end else if (SET) begin
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q_reg <= 1'b1;
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end else begin
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q_reg <= D;
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end
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assign Q = q_reg;
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - asynchronous active high reset
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// - asynchronous active high set
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// - scan-chain input
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// - a scan-chain enable
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//-----------------------------------------------------
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module SDFFSR (
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input SET, // Set input
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input RST, // Reset input
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input CK, // Clock Input
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input SE, // Scan-chain Enable
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input D, // Data Input
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input SI, // Scan-chain input
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output Q, // Q output
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output QN // Q negative output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge CK or posedge RST or posedge SET)
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if (RST) begin
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q_reg <= 1'b0;
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end else if (SET) begin
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q_reg <= 1'b1;
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end else if (SE) begin
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q_reg <= SI;
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end else begin
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q_reg <= D;
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end
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - asynchronous active high reset
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// - scan-chain input
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// - a scan-chain enable
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//-----------------------------------------------------
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module SDFFRQ (
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input RST, // Reset input
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input CK, // Clock Input
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input SE, // Scan-chain Enable
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input D, // Data Input
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input SI, // Scan-chain input
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output Q // Q output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge CK or posedge RST)
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if (RST) begin
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q_reg <= 1'b0;
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end else if (SE) begin
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q_reg <= SI;
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end else begin
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q_reg <= D;
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end
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assign Q = q_reg;
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - asynchronous active high reset
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// - asynchronous active high set
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// - scan-chain input
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// - a scan-chain enable
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//-----------------------------------------------------
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module SDFFSRQ (
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input SET, // Set input
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input RST, // Reset input
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input CK, // Clock Input
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input SE, // Scan-chain Enable
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input D, // Data Input
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input SI, // Scan-chain input
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output Q // Q output
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);
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//------------Internal Variables--------
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reg q_reg;
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//-------------Code Starts Here---------
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always @ ( posedge CK or posedge RST or posedge SET)
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if (RST) begin
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q_reg <= 1'b0;
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end else if (SET) begin
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q_reg <= 1'b1;
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end else if (SE) begin
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q_reg <= SI;
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end else begin
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q_reg <= D;
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end
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assign Q = q_reg;
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endmodule //End Of Module
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//-----------------------------------------------------
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// Function : D-type flip-flop with
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// - asynchronous active high reset
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// - scan-chain input
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// - a scan-chain enable
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// - a configure enable, when enabled the registered output will
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// be released to the Q
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//-----------------------------------------------------
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module CFGSDFFR (
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input RST, // Reset input
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input CK, // Clock Input
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input SE, // Scan-chain Enable
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input D, // Data Input
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input SI, // Scan-chain input
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input CFGE, // Configure enable
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output Q, // Regular Q output
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output CFGQ, // Data Q output which is released when configure enable is activated
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output CFGQN // Data Qb output which is released when configure enable is activated
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);
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//------------Internal Variables--------
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reg q_reg;
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wire QN;
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//-------------Code Starts Here---------
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always @ ( posedge CK or posedge RST)
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if (RST) begin
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q_reg <= 1'b0;
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end else if (SE) begin
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q_reg <= SI;
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end else begin
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q_reg <= D;
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end
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assign CFGQ = CFGE ? Q : 1'b0;
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assign CFGQN = CFGE ? QN : 1'b1;
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endmodule //End Of Module
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@ -1,29 +1,9 @@
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// ----- Verilog module for INVTX1 -----
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module INVTX1(in,
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out);
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//----- INPUT PORTS -----
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module INVTX1(in, out);
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input [0:0] in;
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//----- OUTPUT PORTS -----
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output [0:0] out;
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//----- BEGIN wire-connection ports -----
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//----- END wire-connection ports -----
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//----- BEGIN Registered ports -----
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//----- END Registered ports -----
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// ----- Verilog codes of a regular inverter -----
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//assign out = (in === 1'bz)? $random : ~in;
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assign out = ~in;
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`ifdef ENABLE_TIMING
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// ------ BEGIN Pin-to-pin Timing constraints -----
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specify
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(in[0] => out[0]) = (0.01, 0.01);
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endspecify
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// ------ END Pin-to-pin Timing constraints -----
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`endif
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endmodule
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// ----- END Verilog module for INVTX1 -----
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