From 95fe4d7dae866f98038edbc8c862449293e46bfe Mon Sep 17 00:00:00 2001
From: Nachiket Kapre <nachiket@uwaterloo.ca>
Date: Tue, 9 Feb 2021 10:34:54 -0500
Subject: [PATCH] adding dff synth

---
 .../openfpga_cell_library/verilog/dffsynth.v  | 360 ++++++++++++++++++
 .../openfpga_cell_library/verilog/inv.v       |  26 +-
 2 files changed, 363 insertions(+), 23 deletions(-)
 create mode 100644 openfpga_flow/openfpga_cell_library/verilog/dffsynth.v

diff --git a/openfpga_flow/openfpga_cell_library/verilog/dffsynth.v b/openfpga_flow/openfpga_cell_library/verilog/dffsynth.v
new file mode 100644
index 000000000..c97da167b
--- /dev/null
+++ b/openfpga_flow/openfpga_cell_library/verilog/dffsynth.v
@@ -0,0 +1,360 @@
+//-----------------------------------------------------
+// Design Name : D-type Flip-flops
+// File Name   : ff.v
+// Coder       : Xifan TANG
+//-----------------------------------------------------
+
+//-----------------------------------------------------
+// Function    : A native D-type flip-flop with single output
+//-----------------------------------------------------
+module DFFQ (
+  input CK, // Clock Input
+  input D, // Data Input
+  output Q // Q output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ (posedge CK) begin 
+  q_reg <= D;
+end
+
+endmodule //End Of Module
+
+//-----------------------------------------------------
+// Function    : A native D-type flip-flop
+//-----------------------------------------------------
+module DFF (
+  input CK, // Clock Input
+  input D, // Data Input
+  output Q, // Q output
+  output QN // QB output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ (posedge CK) begin 
+  q_reg <= D;
+end
+
+endmodule //End Of Module
+
+//-----------------------------------------------------
+// Function    : D-type flip-flop with 
+//               - single output
+//               - asynchronous active high reset
+//-----------------------------------------------------
+module DFFRQ (
+  input RST, // Reset input
+  input CK, // Clock Input
+  input D, // Data Input
+  output Q // Q output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ ( posedge CK or posedge RST)
+if (RST) begin
+  q_reg <= 1'b0;
+end else begin
+  q_reg <= D;
+end
+
+endmodule //End Of Module
+
+
+//-----------------------------------------------------
+// Function    : D-type flip-flop with 
+//               - asynchronous active high reset
+//-----------------------------------------------------
+module DFFR (
+  input RST, // Reset input
+  input CK, // Clock Input
+  input D, // Data Input
+  output Q, // Q output
+  output QN // QB output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ ( posedge CK or posedge RST)
+if (RST) begin
+  q_reg <= 1'b0;
+end else begin
+  q_reg <= D;
+end
+
+endmodule //End Of Module
+
+//-----------------------------------------------------
+// Function    : D-type flip-flop with 
+//               - asynchronous active low reset
+//-----------------------------------------------------
+module DFFRN (
+  input RSTN, // Reset input
+  input CK, // Clock Input
+  input D, // Data Input
+  output Q, // Q output
+  output QN // QB output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ ( posedge CK or negedge RSTN)
+if (~RSTN) begin
+  q_reg <= 1'b0;
+end else begin
+  q_reg <= D;
+end
+
+endmodule //End Of Module
+
+
+//-----------------------------------------------------
+// Function    : D-type flip-flop with 
+//               - asynchronous active high set
+//-----------------------------------------------------
+module DFFS (
+  input SET, // Set input
+  input CK, // Clock Input
+  input D, // Data Input
+  output Q, // Q output
+  output QN // QB output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ ( posedge CK or posedge SET)
+if (SET) begin
+  q_reg <= 1'b1;
+end else begin
+  q_reg <= D;
+end
+
+endmodule //End Of Module
+
+//-----------------------------------------------------
+// Function    : D-type flip-flop with 
+//               - asynchronous active low set
+//-----------------------------------------------------
+module DFFSN (
+  input SETN, // Set input
+  input CK, // Clock Input
+  input D, // Data Input
+  output Q, // Q output
+  output QN // QB output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ ( posedge CK or negedge SETN)
+if (~SETN) begin
+  q_reg <= 1'b1;
+end else begin
+  q_reg <= D;
+end
+
+endmodule //End Of Module
+
+
+//-----------------------------------------------------
+// Function    : D-type flip-flop with 
+//               - asynchronous active high reset
+//               - asynchronous active high set
+//-----------------------------------------------------
+module DFFSR (
+  input SET, // set input
+  input RST, // Reset input
+  input CK, // Clock Input
+  input D, // Data Input
+  output Q, // Q output
+  output QN // QB output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ ( posedge CK or posedge RST or posedge SET)
+if (RST) begin
+  q_reg <= 1'b0;
+end else if (SET) begin
+  q_reg <= 1'b1;
+end else begin
+  q_reg <= D;
+end
+
+endmodule //End Of Module
+
+//-----------------------------------------------------
+// Function    : D-type flip-flop with 
+//               - asynchronous active high reset
+//               - asynchronous active high set
+//-----------------------------------------------------
+module DFFSRQ (
+  input SET, // set input
+  input RST, // Reset input
+  input CK, // Clock Input
+  input D, // Data Input
+  output Q // Q output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ ( posedge CK or posedge RST or posedge SET)
+if (RST) begin
+  q_reg <= 1'b0;
+end else if (SET) begin
+  q_reg <= 1'b1;
+end else begin
+  q_reg <= D;
+end
+
+assign Q = q_reg;
+
+endmodule //End Of Module
+
+//-----------------------------------------------------
+// Function    : D-type flip-flop with 
+//               - asynchronous active high reset
+//               - asynchronous active high set
+//               - scan-chain input
+//               - a scan-chain enable 
+//-----------------------------------------------------
+module SDFFSR (
+  input SET, // Set input
+  input RST, // Reset input
+  input CK, // Clock Input
+  input SE, // Scan-chain Enable
+  input D, // Data Input
+  input SI, // Scan-chain input
+  output Q, // Q output
+  output QN // Q negative output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ ( posedge CK or posedge RST or posedge SET)
+if (RST) begin
+  q_reg <= 1'b0;
+end else if (SET) begin
+  q_reg <= 1'b1;
+end else if (SE) begin
+  q_reg <= SI;
+end else begin
+  q_reg <= D;
+end
+
+endmodule //End Of Module
+
+//-----------------------------------------------------
+// Function    : D-type flip-flop with 
+//               - asynchronous active high reset
+//               - scan-chain input
+//               - a scan-chain enable 
+//-----------------------------------------------------
+module SDFFRQ (
+  input RST, // Reset input
+  input CK, // Clock Input
+  input SE, // Scan-chain Enable
+  input D, // Data Input
+  input SI, // Scan-chain input
+  output Q // Q output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ ( posedge CK or posedge RST)
+if (RST) begin
+  q_reg <= 1'b0;
+end else if (SE) begin
+  q_reg <= SI;
+end else begin
+  q_reg <= D;
+end
+
+assign Q = q_reg;
+
+endmodule //End Of Module
+
+//-----------------------------------------------------
+// Function    : D-type flip-flop with 
+//               - asynchronous active high reset
+//               - asynchronous active high set
+//               - scan-chain input
+//               - a scan-chain enable 
+//-----------------------------------------------------
+module SDFFSRQ (
+  input SET, // Set input
+  input RST, // Reset input
+  input CK, // Clock Input
+  input SE, // Scan-chain Enable
+  input D, // Data Input
+  input SI, // Scan-chain input
+  output Q // Q output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ ( posedge CK or posedge RST or posedge SET)
+if (RST) begin
+  q_reg <= 1'b0;
+end else if (SET) begin
+  q_reg <= 1'b1;
+end else if (SE) begin
+  q_reg <= SI;
+end else begin
+  q_reg <= D;
+end
+
+assign Q = q_reg;
+
+endmodule //End Of Module
+
+//-----------------------------------------------------
+// Function    : D-type flip-flop with 
+//               - asynchronous active high reset
+//               - scan-chain input
+//               - a scan-chain enable 
+//               - a configure enable, when enabled the registered output will
+//               be released to the Q
+//-----------------------------------------------------
+module CFGSDFFR (
+  input RST, // Reset input
+  input CK, // Clock Input
+  input SE, // Scan-chain Enable
+  input D, // Data Input
+  input SI, // Scan-chain input
+  input CFGE, // Configure enable
+  output Q, // Regular Q output
+  output CFGQ, // Data Q output which is released when configure enable is activated
+  output CFGQN // Data Qb output which is released when configure enable is activated
+);
+//------------Internal Variables--------
+reg q_reg;
+wire QN;
+
+//-------------Code Starts Here---------
+always @ ( posedge CK or posedge RST)
+if (RST) begin
+  q_reg <= 1'b0;
+end else if (SE) begin
+  q_reg <= SI;
+end else begin
+  q_reg <= D;
+end
+
+assign CFGQ = CFGE ? Q : 1'b0;
+assign CFGQN = CFGE ? QN : 1'b1;
+
+endmodule //End Of Module
diff --git a/openfpga_flow/openfpga_cell_library/verilog/inv.v b/openfpga_flow/openfpga_cell_library/verilog/inv.v
index cb208248f..f62e59f33 100644
--- a/openfpga_flow/openfpga_cell_library/verilog/inv.v
+++ b/openfpga_flow/openfpga_cell_library/verilog/inv.v
@@ -1,29 +1,9 @@
 // ----- Verilog module for INVTX1 -----
-module INVTX1(in,
-              out);
-//----- INPUT PORTS -----
-input [0:0] in;
-//----- OUTPUT PORTS -----
-output [0:0] out;
+module INVTX1(in, out);
+  input [0:0] in;
+  output [0:0] out;
 
-//----- BEGIN wire-connection ports -----
-//----- END wire-connection ports -----
-
-
-//----- BEGIN Registered ports -----
-//----- END Registered ports -----
-
-// ----- Verilog codes of a regular inverter -----
-  //assign out = (in === 1'bz)? $random : ~in;
   assign out = ~in;
 
-`ifdef ENABLE_TIMING
-// ------ BEGIN Pin-to-pin Timing constraints -----
-  specify
-    (in[0] => out[0]) = (0.01, 0.01);
-  endspecify
-// ------ END Pin-to-pin Timing constraints -----
-`endif
 endmodule
-// ----- END Verilog module for INVTX1 -----