riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

bug fix in the regression test due to benchmark changes

This commit is contained in:
tangxifan 2020-07-22 13:17:05 -06:00
parent 05dccadf21
commit 92c3449999
2 changed files with 3 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
openfpga_flow/benchmarks/micro_benchmark/counter/counter.v
View File

@ -1,4 +1,4 @@
module counter_original(clk_counter, q_counter, rst_counter);
module counter(clk_counter, q_counter, rst_counter);
input clk_counter;
input rst_counter;

6
openfpga_flow/tasks/implicit_verilog/config/task.conf
View File

@ -14,7 +14,7 @@ power_analysis = true
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=vpr_blif
fpga_flow=yosys_vpr
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
external_fabric_key_file=
@ -23,12 +23,10 @@ external_fabric_key_file=
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_post_yosys.blif
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v
[SYNTHESIS_PARAM]
bench0_top = counter
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_pre_vpr.act
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_output_verilog.v
bench0_chan_width = 300
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]