diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v
index 98a4ff291..216053285 100644
--- a/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v
+++ b/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v
@@ -1,4 +1,4 @@
-module counter_original(clk_counter, q_counter, rst_counter);
+module counter(clk_counter, q_counter, rst_counter);
 
     input clk_counter;
     input rst_counter;
diff --git a/openfpga_flow/tasks/implicit_verilog/config/task.conf b/openfpga_flow/tasks/implicit_verilog/config/task.conf
index 5ebdd49a7..6c94a415a 100644
--- a/openfpga_flow/tasks/implicit_verilog/config/task.conf
+++ b/openfpga_flow/tasks/implicit_verilog/config/task.conf
@@ -14,7 +14,7 @@ power_analysis = true
 spice_output=false
 verilog_output=true
 timeout_each_job = 20*60
-fpga_flow=vpr_blif
+fpga_flow=yosys_vpr
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 external_fabric_key_file=
@@ -23,12 +23,10 @@ external_fabric_key_file=
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_post_yosys.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v
 
 [SYNTHESIS_PARAM]
 bench0_top = counter
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_pre_vpr.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter_output_verilog.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]