[FPGA-Verilog] Fixed a bug on the non-inverted reset signal in testbenches when pin constraints are provided
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0a449cc24c
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@ -143,6 +143,7 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
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const std::string& circuit_name,
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const std::string& circuit_name,
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const AtomContext& atom_ctx,
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const AtomContext& atom_ctx,
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const VprNetlistAnnotation& netlist_annotation,
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const VprNetlistAnnotation& netlist_annotation,
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const PinConstraints& pin_constraints,
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const bool& explicit_port_mapping) {
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const bool& explicit_port_mapping) {
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/* Validate the file stream */
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/* Validate the file stream */
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valid_file_stream(fp);
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valid_file_stream(fp);
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@ -157,7 +158,7 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp,
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std::vector<std::string>(),
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std::vector<std::string>(),
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std::string(FPGA_PORT_POSTFIX),
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std::string(FPGA_PORT_POSTFIX),
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atom_ctx, netlist_annotation,
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atom_ctx, netlist_annotation,
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PinConstraints(),
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pin_constraints,
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explicit_port_mapping);
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explicit_port_mapping);
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print_verilog_comment(fp, std::string("----- End FPGA Fabric Instanication -------"));
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print_verilog_comment(fp, std::string("----- End FPGA Fabric Instanication -------"));
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@ -301,6 +302,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
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/* Call defined top-level module */
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/* Call defined top-level module */
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print_verilog_random_testbench_fpga_instance(fp, circuit_name,
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print_verilog_random_testbench_fpga_instance(fp, circuit_name,
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atom_ctx, netlist_annotation,
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atom_ctx, netlist_annotation,
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pin_constraints,
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options.explicit_port_mapping());
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options.explicit_port_mapping());
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/* Call defined benchmark */
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/* Call defined benchmark */
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