From 91627abe12986b0dda6daf6f2452c8072c801d9c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 30 Oct 2021 11:53:46 -0700 Subject: [PATCH] [FPGA-Verilog] Fixed a bug on the non-inverted reset signal in testbenches when pin constraints are provided --- .../src/fpga_verilog/verilog_formal_random_top_testbench.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp index 47fc6a13d..3e620cec5 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp @@ -143,6 +143,7 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp, const std::string& circuit_name, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const PinConstraints& pin_constraints, const bool& explicit_port_mapping) { /* Validate the file stream */ valid_file_stream(fp); @@ -157,7 +158,7 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp, std::vector(), std::string(FPGA_PORT_POSTFIX), atom_ctx, netlist_annotation, - PinConstraints(), + pin_constraints, explicit_port_mapping); print_verilog_comment(fp, std::string("----- End FPGA Fabric Instanication -------")); @@ -301,6 +302,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name, /* Call defined top-level module */ print_verilog_random_testbench_fpga_instance(fp, circuit_name, atom_ctx, netlist_annotation, + pin_constraints, options.explicit_port_mapping()); /* Call defined benchmark */