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[HDL] Bug fix in HDL modeling of multi-mode 16-bit DSP block

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tangxifan 2021-04-24 14:57:09 -06:00
parent a3a98fa21d
commit 8b8096f3a8
1 changed files with 1 additions and 1 deletions
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openfpga_flow/openfpga_cell_library/verilog/frac_mult_16x16.v
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@ -13,7 +13,7 @@ module frac_mult_16x16 (
output [0:31] out, output [0:31] out,
input [0:0] mode); input [0:0] mode);
reg [0:63] out_reg; reg [0:31] out_reg;
always @(mode, a, b) begin always @(mode, a, b) begin
if (1'b1 == mode) begin if (1'b1 == mode) begin