From 8b8096f3a860e655ebebd644f8673a3b5c2e11cc Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 24 Apr 2021 14:57:09 -0600 Subject: [PATCH] [HDL] Bug fix in HDL modeling of multi-mode 16-bit DSP block --- openfpga_flow/openfpga_cell_library/verilog/frac_mult_16x16.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_cell_library/verilog/frac_mult_16x16.v b/openfpga_flow/openfpga_cell_library/verilog/frac_mult_16x16.v index 7fedc711c..d73a1c7e1 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/frac_mult_16x16.v +++ b/openfpga_flow/openfpga_cell_library/verilog/frac_mult_16x16.v @@ -13,7 +13,7 @@ module frac_mult_16x16 ( output [0:31] out, input [0:0] mode); - reg [0:63] out_reg; + reg [0:31] out_reg; always @(mode, a, b) begin if (1'b1 == mode) begin