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[Flow] Rename the design contraint file syntax

This commit is contained in:
tangxifan 2021-01-16 15:35:13 -07:00
parent 9154cfdeec
commit 8578c1ecac
1 changed files with 4 additions and 4 deletions
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8
openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml
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@ -6,9 +6,9 @@
- the clk[2] port of all the clb tiles available in the FPGA fabric
- the clk[3] port of all the clb tiles available in the FPGA fabric
-->
<pin_constraint tile="clb" name="clk[0]" net="clk0"/>
<pin_constraint tile="clb" name="clk[1]" net="clk1"/>
<pin_constraint tile="clb" name="clk[2]" net="OPEN"/>
<pin_constraint tile="clb" name="clk[3]" net="OPEN"/>
<pin_constraint tile="clb" pin="clk[0]" net="clk0"/>
<pin_constraint tile="clb" pin="clk[1]" net="clk1"/>
<pin_constraint tile="clb" pin="clk[2]" net="OPEN"/>
<pin_constraint tile="clb" pin="clk[3]" net="OPEN"/>
</repack_pin_constraints>