diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml
index 31f0473f3..ed4a49775 100644
--- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml
+++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml
@@ -6,9 +6,9 @@
        - the clk[2] port of all the clb tiles available in the FPGA fabric
        - the clk[3] port of all the clb tiles available in the FPGA fabric
     -->
-  <pin_constraint tile="clb" name="clk[0]" net="clk0"/>
-  <pin_constraint tile="clb" name="clk[1]" net="clk1"/>
-  <pin_constraint tile="clb" name="clk[2]" net="OPEN"/>
-  <pin_constraint tile="clb" name="clk[3]" net="OPEN"/>
+  <pin_constraint tile="clb" pin="clk[0]" net="clk0"/>
+  <pin_constraint tile="clb" pin="clk[1]" net="clk1"/>
+  <pin_constraint tile="clb" pin="clk[2]" net="OPEN"/>
+  <pin_constraint tile="clb" pin="clk[3]" net="OPEN"/>
 </repack_pin_constraints>