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16 bit adder chain working

This commit is contained in:
Andrew Pond 2021-10-21 09:55:57 -06:00
parent a486c2690f
commit 7f31f527a4
14 changed files with 1884 additions and 17 deletions
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2
openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v
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// Creating a scaleable adder // Creating a scaleable adder
module adder_16(cout, sum, a, b, cin); module adder_16(cout, sum, a, b, cin);
parameter size = 6; /* declare a parameter. default required */ parameter size = 3; /* declare a parameter. default required */
output cout; output cout;
output [size-1:0] sum; // sum uses the size parameter output [size-1:0] sum; // sum uses the size parameter
input cin; input cin;

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openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16_clk.v Normal file
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// Creating a scaleable adder
module adder_16_clk #(
parameter size = 2
)(
output reg cout,
output reg [size-1:0] sum, // sum uses the size parameter
input cin,
input [size-1:0] a, b, // 'a' and 'b' use the size parameter
input clk_in,
input rst
);
// reg [size-1:0] _sum;
// reg _cout;
always @(posedge clk_in) begin
if (rst)
{sum,cout} <= 0;
else
{sum,cout} <= a + b + cin;
end
// assign sum = _sum;
// assign cout = _cout;
// assign {cout, sum} = a + b + cin;
endmodule

41
openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/wrapper.v Normal file
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module adder_16_wrapper(
output cout,
output sum_0,
output sum_1,
output sum_2,
output sum_3,
input cin,
input a_0,
input a_1,
input a_2,
input a_3,
input b_0,
input b_1,
input b_2,
input b_3
);
wire [4:0] sum;
assign sum_0 = sum[0];
assign sum_1 = sum[1];
assign sum_2 = sum[2];
assign sum_3 = sum[3];
wire [4:0] a;
assign a_0 = a[0];
assign a_1 = a[1];
assign a_2 = a[2];
assign a_3 = a[3];
wire [4:0] b;
assign b_0 = b[0];
assign b_1 = b[1];
assign b_2 = b[2];
assign b_3 = b[3];
adder_16 DUT(
.cout(cout),
.sum(sum),
.cin(cin),
.a(a),
.b(b) );
endmodule

1177
openfpga_flow/misc/1k_bram.xml Normal file
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352
openfpga_flow/misc/1k_bram_openfpga.xml Normal file
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<!-- Architecture annotation for OpenFPGA framework
This annotation supports the k4_frac_cc_sky130nm.xml
- General purpose logic block
- K = 4, N = 8, I = 24
- Routing architecture
- 10% L = 1, fc_in = 0.15, Fc_out = 0.10
- 10% L = 2, fc_in = 0.15, Fc_out = 0.10
- 80% L = 4, fc_in = 0.15, Fc_out = 0.10
- DSP block:
- Multi-mode multiplier which can operate in two modes
- Mode A: 18-bit multiplier
- Mode B: two independent 9-bit multipliers
- Skywater 130nm PDK
- circuit models are binded to the opensource skywater
foundry high-density standard cell library
-->
<openfpga_architecture>
<technology_library>
<device_library>
<device_model name="logic" type="transistor">
<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<design vdd="0.9" pn_ratio="2"/>
<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
</device_model>
<device_model name="io" type="transistor">
<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
<design vdd="2.5" pn_ratio="3"/>
<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
</device_model>
</device_library>
<variation_library>
<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
</variation_library>
</technology_library>
<circuit_library>
<!-- Dummy Circuit model -->
<circuit_model type="inv_buf" name="inv_01" prefix="inv_01" verilog_netlist="./SRC/sc_verilog/simulationCells.v">
<design_technology type="cmos" topology="inverter" size="1"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="Y" size="1"/>
</circuit_model>
<!-- Dummy Circuit model -->
<circuit_model type="inv_buf" name="inv_02" prefix="inv_02" verilog_netlist="./SRC/CustomModules/sky130_fd_sc_hd_wrapper.v">
<design_technology type="cmos" topology="inverter" size="1"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="Y" size="1"/>
</circuit_model>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_1" prefix="sky130_fd_sc_hd__inv_1" is_default="true" verilog_netlist="./SRC/sc_verilog/simulationCells.v">
<design_technology type="cmos" topology="inverter" size="1"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="Y" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_2" prefix="sky130_fd_sc_hd__buf_2" is_default="false" verilog_netlist="./SRC/sc_verilog/simulationCells.v">
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="2"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="X" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__buf_4" prefix="sky130_fd_sc_hd__buf_4" is_default="false" verilog_netlist="./SRC/sc_verilog/simulationCells.v">
<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="X" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="inv_buf" name="sky130_fd_sc_hd__inv_2" prefix="sky130_fd_sc_hd__inv_2" is_default="false" verilog_netlist="./SRC/sc_verilog/simulationCells.v">
<design_technology type="cmos" topology="buffer" size="1"/>
<device_technology device_model_name="logic"/>
<port type="input" prefix="in" lib_name="A" size="1"/>
<port type="output" prefix="out" lib_name="Y" size="1"/>
<delay_matrix type="rise" in_port="in" out_port="out">
10e-12
</delay_matrix>
<delay_matrix type="fall" in_port="in" out_port="out">
10e-12
</delay_matrix>
</circuit_model>
<circuit_model type="gate" name="sky130_fd_sc_hd__or2_1" prefix="sky130_fd_sc_hd__or2_1" is_default="true" verilog_netlist="./SRC/sc_verilog/simulationCells.v">
<design_technology type="cmos" topology="OR"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="a" lib_name="A" size="1"/>
<port type="input" prefix="b" lib_name="B" size="1"/>
<port type="output" prefix="out" lib_name="X" size="1"/>
<delay_matrix type="rise" in_port="a b" out_port="out">
10e-12 5e-12
</delay_matrix>
<delay_matrix type="fall" in_port="a b" out_port="out">
10e-12 5e-12
</delay_matrix>
</circuit_model>
<!-- Define a circuit model for the standard cell MUX2
OpenFPGA requires the following truth table for the MUX2
When the select signal sel is enabled, the first input, i.e., in0
will be propagated to the output, i.e., out
If your standard cell provider does not offer the exact truth table,
you can simply swap the inputs as shown in the example below
-->
<circuit_model type="gate" name="sky130_fd_sc_hd__mux2_1" prefix="sky130_fd_sc_hd__mux2_1" verilog_netlist="./SRC/sc_verilog/simulationCells.v">
<design_technology type="cmos" topology="MUX2"/>
<device_technology device_model_name="logic"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in0" lib_name="A1" size="1"/>
<port type="input" prefix="in1" lib_name="A0" size="1"/>
<port type="input" prefix="sel" lib_name="S" size="1"/>
<port type="output" prefix="out" lib_name="X" size="1"/>
</circuit_model>
<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
<design_technology type="cmos"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/>
<!-- model_type could be T, res_val and cap_val DON'T CARE -->
</circuit_model>
<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
<design_technology type="cmos"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<wire_param model_type="pi" R="0" C="0" num_level="1"/>
<!-- model_type could be T, res_val cap_val should be defined -->
</circuit_model>
<circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
<input_buffer exist="false"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_4"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/>
</circuit_model>
<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
<circuit_model type="ff" name="sofa_plus_dff" prefix="sofa_plus_dff" verilog_netlist="./SRC/CustomModules/sofa_plus_dff.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="DI" size="1"/>
<port type="input" prefix="Test_en" size="1" is_global="true" default_val="0"/>
<port type="input" prefix="R" size="1" default_val="0"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="C" size="1" default_val="0" />
<port type="sram" prefix="MODE_SEL" size="2" mode_select="true" circuit_model_name="sofa_plus_ccff" default_val="0"/>
</circuit_model>
<circuit_model type="lut" name="frac_lut4_arith" prefix="frac_lut4_arith" dump_structural_verilog="true" verilog_netlist="./SRC/CustomModules/frac_lut4_arith.v">
<design_technology type="cmos" fracturable_lut="true"/>
<input_buffer exist="false"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
<lut_input_inverter exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<lut_input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2"/>
<lut_intermediate_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__buf_2" location_map="-1-"/>
<pass_gate_logic circuit_model_name="sky130_fd_sc_hd__mux2_1"/>
<port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="sky130_fd_sc_hd__or2_1"/>
<port type="input" prefix="cin" size="1" is_harden_lut_port="true"/>
<port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
<port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
<port type="output" prefix="cout" size="1" is_harden_lut_port="true"/>
<port type="sram" prefix="sram" size="16"/>
<port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sofa_plus_ccff" default_val="1"/>
</circuit_model>
<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
<circuit_model type="ccff" name="sofa_plus_ccff" prefix="sofa_plus_ccff" verilog_netlist="./SRC/CustomModules/sofa_plus_ccff.v">
<design_technology type="cmos"/>
<input_buffer exist="false"/>
<output_buffer exist="false"/>
<port type="input" prefix="D" size="1"/>
<port type="input" prefix="scan_data_in" lib_name="SI" size="1"/>
<!-- This port allows readback configurable memories without modifying the storage -->
<!-- <port type="input" prefix="config_readback" lib_name="SCE" size="1" is_global="true" default_val="0"/> -->
<!-- This port allows programming circuitry is be isolated from datapath logic during programming -->
<port type="input" prefix="config_enable" lib_name="CFGE" size="1" is_global="true" default_val="0" is_config_enable="true"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="CFGQN" size="1"/>
<port type="output" prefix="CFGQ" size="1"/>
<port type="clock" prefix="prog_clk" lib_name="CLK" size="1" is_global="true" default_val="0" is_prog="true"/>
<port type="input" prefix="pReset" lib_name="RESET_B" size="1" is_global="true" default_val="1" is_prog="true" is_reset="true"/>
</circuit_model>
<circuit_model type="iopad" name="sofa_plus_io" prefix="sofa_plus_io" is_default="true" verilog_netlist="./SRC/CustomModules/sofa_plus_io.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<output_buffer exist="true" circuit_model_name="sky130_fd_sc_hd__inv_1"/>
<port type="input" prefix="SOC_IN" lib_name="SOC_IN" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="output" prefix="SOC_OUT" lib_name="SOC_OUT" size="1" is_global="true" is_io="true" is_data_io="true"/>
<port type="output" prefix="SOC_DIR" lib_name="SOC_DIR" size="1" is_global="true" is_io="true"/>
<port type="input" prefix="IO_ISOL_N" lib_name="IO_ISOL_N" size="1" is_global="true" default_val="1"/>
<port type="output" prefix="inpad" lib_name="FPGA_IN" size="1"/>
<port type="input" prefix="outpad" lib_name="FPGA_OUT" size="1"/>
<port type="sram" prefix="en" lib_name="FPGA_DIR" size="1" mode_select="true" circuit_model_name="sofa_plus_ccff" default_val="1"/>
</circuit_model>
<circuit_model type="hard_logic" name="frac_mult_18_18" prefix="frac_mult_18_18" is_default="true" verilog_netlist="./SRC/CustomModules/frac_mult_18_18.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="A" lib_name="A" size="18"/>
<port type="input" prefix="B" lib_name="B" size="18"/>
<port type="output" prefix="Y" lib_name="Y" size="36"/>
<port type="sram" prefix="mode" lib_name="MODE" size="1" mode_select="true" circuit_model_name="sofa_plus_ccff" default_val="1"/>
</circuit_model>
<circuit_model type="hard_logic" name="dpram_128x8" prefix="dpram_128x8" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dpram1k.v">
<design_technology type="cmos"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/>
<port type="input" prefix="waddr" size="7"/>
<port type="input" prefix="raddr" size="7"/>
<port type="input" prefix="data_in" size="8"/>
<port type="input" prefix="wen" size="1"/>
<port type="input" prefix="ren" size="1"/>
<port type="output" prefix="data_out" size="8"/>
<port type="clock" prefix="clk" size="1"/>
</circuit_model>
</circuit_library>
<configuration_protocol>
<organization type="scan_chain" circuit_model_name="sofa_plus_ccff" num_regions="12"/>
</configuration_protocol>
<connection_block>
<switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
</connection_block>
<switch_block>
<switch name="L1_mux" circuit_model_name="mux_tree_tapbuf"/>
<switch name="L2_mux" circuit_model_name="mux_tree_tapbuf"/>
<switch name="L4_mux" circuit_model_name="mux_tree_tapbuf"/>
</switch_block>
<routing_segment>
<segment name="L1" circuit_model_name="chan_segment"/>
<segment name="L2" circuit_model_name="chan_segment"/>
<segment name="L4" circuit_model_name="chan_segment"/>
</routing_segment>
<direct_connection>
<direct name="carry_chain" circuit_model_name="direct_interc"/>
<direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
</direct_connection>
<tile_annotations>
<global_port name="clk" is_clock="true" default_val="0">
<tile name="clb" port="clk" x="-1" y="-1"/>
<tile name="memory" port="clk"/>
</global_port>
<global_port name="reset" is_reset="true" default_val="0">
<tile name="clb" port="reset" x="-1" y="-1"/>
</global_port>
</tile_annotations>
<pb_type_annotations>
<!-- physical pb_type binding in complex block IO -->
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
<!-- IMPORTANT: must set unused I/Os to operating in INPUT mode !!! -->
<pb_type name="io[physical].iopad" circuit_model_name="sofa_plus_io" mode_bits="1"/>
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
<!-- End physical pb_type binding in complex block IO -->
<!-- physical pb_type binding in complex block CLB -->
<!-- physical mode will be the default mode if not specified -->
<pb_type name="clb.fle" physical_mode_name="physical"/>
<pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4_arith" circuit_model_name="frac_lut4_arith" mode_bits="00"/>
<pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="sofa_plus_dff" mode_bits="00"/>
<!-- Binding operating pb_type to physical pb_type -->
<!-- Binding operating pb_types in mode 'arithmetic' -->
<pb_type name="clb.fle[arithmetic].soft_adder.adder_lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4_arith" mode_bits="11"/>
<!-- Binding operating pb_types in mode 'n2_lut3' -->
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4_arith" mode_bits="01" physical_pb_type_index_factor="0.5">
<!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
<port name="in" physical_mode_port="in[0:2]"/>
<port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
</pb_type>
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00">
<port name="clk" physical_mode_port="C"/>
</pb_type>
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00"/>
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00"/>
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="10">
<port name="RN" physical_mode_port="R"/>
</pb_type>
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffs].dffs" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="01">
<port name="S" physical_mode_port="R"/>
</pb_type>
<pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff[dffsn].dffsn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="11">
<port name="SN" physical_mode_port="R"/>
</pb_type>
<!-- Binding operating pb_types in mode 'ble4' -->
<pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4_arith" mode_bits="00">
<!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
<port name="in" physical_mode_port="in[0:3]"/>
<port name="out" physical_mode_port="lut4_out"/>
</pb_type>
<pb_type name="clb.fle[n1_lut4].ble4.ff[latch].latch" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
<port name="clk" physical_mode_port="C"/>
</pb_type>
<pb_type name="clb.fle[n1_lut4].ble4.ff[dff].dff" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
<pb_type name="clb.fle[n1_lut4].ble4.ff[dffr].dffr" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="00" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
<pb_type name="clb.fle[n1_lut4].ble4.ff[dffrn].dffrn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="10" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
<port name="RN" physical_mode_port="R"/>
</pb_type>
<pb_type name="clb.fle[n1_lut4].ble4.ff[dffs].dffs" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="01" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
<port name="S" physical_mode_port="R"/>
</pb_type>
<pb_type name="clb.fle[n1_lut4].ble4.ff[dffsn].dffsn" physical_pb_type_name="clb.fle[physical].fabric.ff" mode_bits="11" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0">
<port name="SN" physical_mode_port="R"/>
</pb_type>
<!-- End physical pb_type binding in complex block CLB -->
<!-- physical pb_type binding in complex block dsp -->
<pb_type name="mult_18.mult_18_core" physical_mode_name="mult_18x18"/>
<!-- Bind the primitive pb_type in the physical mode to a circuit model -->
<pb_type name="mult_18.mult_18_core[mult_18x18].mult_18x18_slice.mult_18x18" circuit_model_name="frac_mult_18_18" mode_bits="0"/>
<pb_type name="mult_18.mult_18_core[mult_9x9].mult_9x9_slice.mult_9x9" physical_pb_type_name="mult_18.mult_18_core[mult_18x18].mult_18x18_slice.mult_18x18" mode_bits="1" physical_pb_type_index_factor="0">
<port name="A" physical_mode_port="A[0:8]" physical_mode_port_rotate_offset="9"/>
<port name="B" physical_mode_port="B[0:8]" physical_mode_port_rotate_offset="9"/>
<port name="Y" physical_mode_port="Y[0:17]" physical_mode_port_rotate_offset="18"/>
</pb_type>
<!-- physical pb_type binding in complex block memory -->
<pb_type name="memory[mem_128x8_dp].mem_128x8_dp" circuit_model_name="dpram_128x8"/>
<!-- END physical pb_type binding in complex block memory -->
</pb_type_annotations>
</openfpga_architecture>

78
openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys Normal file
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@ -0,0 +1,78 @@
${READ_VERILOG_FILE}
# read_verilog -lib cells_sim.v
hierarchy -check -top ${TOP_MODULE}
proc
# flatten
# tribuf -logic
# deminout
opt_expr
opt_clean
check
opt
wreduce
peepopt
opt_clean
share
# techmap -map +/cmp2lut.v -D LUT_WIDTH=4
opt_expr
opt_clean
# ice40_dsp (if -dsp)
alumacc
opt
fsm
opt -fast
memory -nomap
opt_clean
### BRAM
# memory_bram -rules +/ice40/brams.txt
# techmap -map +/ice40/brams_map.v
# ice40_braminit
### Map
# opt -fast -mux_undef -undriven -fine
# memory_map
# opt -undriven -fine
### map_gates
# techmap -map +/techmap.v -map +/ice40/arith_map.v
techmap -map ${YOSYS_ADDER_MAP_VERILOG}
opt
# abc -dff (only if -retime)
# ice40_opt
### map_ffs
# dffsr2dff
# dff2dffe -direct-match $_DFF_*
# techmap -D NO_LUT -map +/ice40/cells_map.v
# opt_expr -mux_undef
# simplemap
# ice40_ffinit
# ice40_ffssr
# ice40_opt -full
stat
### map_luts
abc -lut ${LUT_SIZE}
# abc (only if -abc2)
# ice40_opt (only if -abc2)
# techmap -map +/ice40/latches_map.v
# simplemap (only if -noabc)
# techmap -map +/gate2lut.v -D LUT_WIDTH=4 (only if -noabc)
# abc -dress -lut 4 (skip if -noabc)
# clean
# ice40_unlut (only if -relut)
# opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3 (only if -relut)
### map_cells
# techmap -map +/ice40/cells_map.v (with -D NO_LUT in vpr mode)
# clean
### check
# hierarchy -check
# stat
# check -noinit
### blif
opt_clean -purge
write_blif -conn -param ${OUTPUT_BLIF}

9
openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys
View File

@ -54,8 +54,6 @@ chtype -set $mul t:$__soft_mul# Extract arithmetic functions
######################### #########################
# Run coarse synthesis # Run coarse synthesis
######################### #########################
# Run a tech map with default library
techmap
alumacc alumacc
share share
opt opt
@ -66,6 +64,11 @@ opt -fast
memory -nomap memory -nomap
opt_clean opt_clean
#########################
# Map $alu to carry chain
#########################
techmap -map ${YOSYS_ADDER_MAP_VERILOG}
######################### #########################
# Map logics to BRAMs # Map logics to BRAMs
######################### #########################
@ -92,6 +95,8 @@ opt_rmdff
opt_clean opt_clean
opt opt
stat
######################### #########################
# Map LUTs # Map LUTs
######################### #########################

2
openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga
View File

@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base # Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options # to debug use --verbose options
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges link_openfpga_arch --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist # Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml check_netlist_naming_conflict --fix --report ./netlist_renaming.xml

2
openfpga_flow/openfpga_shell_scripts/write_full_testbench_no_clk_modeling_example_script.openfpga
View File

@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base # Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options # to debug use --verbose options
link_openfpga_arch --sort_gsb_chan_node_in_edges link_openfpga_arch --activity_file and2_ace_out.act --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist # Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml check_netlist_naming_conflict --fix --report ./netlist_renaming.xml

70
openfpga_flow/openfpga_timing_annotation/design_variables.yml Normal file
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@ -0,0 +1,70 @@
L1_SB_MUX_DELAY: 1.44e-9
L2_SB_MUX_DELAY: 1.44e-9
L4_SB_MUX_DELAY: 1.44e-9
CB_MUX_DELAY: 1.38e-9
L1_WIRE_R: 100
L1_WIRE_C: 1e-12
L2_WIRE_R: 100
L2_WIRE_C: 1e-12
L4_WIRE_R: 100
L4_WIRE_C: 1e-12
INPAD_DELAY: 0.11e-9
OUTPAD_DELAY: 0.11e-9
FF_T_SETUP: 0.39e-9
FF_T_CLK2Q: 0.43e-9
LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
LUT_CIN2LUT3_OUT_DELAY: 1.21e-9
LUT_CIN2LUT4_OUT_DELAY: 1.21e-9
LUT_CIN2COUT_DELAY: 1.21e-9
LUT_IN2COUT_DELAY: 1.21e-9
LUT3_DELAY: 0.92e-9
LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
LUT4_DELAY: 1.21e-9
LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
ADDER_LUT4_CIN2OUT_DELAY: 1.21e-9
ADDER_LUT4_CIN2COUT_DELAY: 1.21e-9
ADDER_LUT4_IN2OUT_DELAY: 1.21e-9
ADDER_LUT4_IN2COUT_DELAY: 1.21e-9
CLB_LR_IN2IN_DELAY: 1.46e-9
CLB_LR_OUT2IN_DELAY: 1.46e-9
MULT9_A2Y_DELAY_MAX: 1.523e-9
MULT9_A2Y_DELAY_MIN: 0.776e-9
MULT9_B2Y_DELAY_MAX: 1.523e-9
MULT9_B2Y_DELAY_MIN: 0.776e-9
MULT18_A2Y_DELAY_MAX: 1.523e-9
MULT18_A2Y_DELAY_MIN: 0.776e-9
MULT18_B2Y_DELAY_MAX: 1.523e-9
MULT18_B2Y_DELAY_MIN: 0.776e-9
MULT18_LR_A2A_DELAY_MAX: 1.46e-9
MULT18_LR_A2A_DELAY_MIN: 1.46e-9
MULT18_LR_B2B_DELAY_MAX: 1.46e-9
MULT18_LR_B2B_DELAY_MIN: 1.46e-9
################# BRAM Delays #################
DPRAM_128x8_CLK_TO_WADDR_DELAY: 509e-12
DPRAM_128x8_CLK_TO_RADDR_DELAY: 509e-12
DPRAM_128x8_CLK_TO_DATA_IN_DELAY: 509e-12
DPRAM_128x8_CLK_TO_WEN_DELAY: 509e-12
DPRAM_128x8_CLK_TO_REN_DELAY: 509e-12
DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 6.73e-9
DPRAM_1024x8_CLK_TO_WADDR_DELAY: 509e-12
DPRAM_1024x8_CLK_TO_RADDR_DELAY: 509e-12
DPRAM_1024x8_CLK_TO_DATA_IN_DELAY: 509e-12
DPRAM_1024x8_CLK_TO_WEN_DELAY: 509e-12
DPRAM_1024x8_CLK_TO_REN_DELAY: 509e-12
DPRAM_1024x8_CLK_TO_DATA_OUT_DELAY: 6.73e-9
MEMORY_WADDR_TO_BRAM_WADDR_DELAY: 132e-12
MEMORY_RADDR_TO_BRAM_RADDR_DELAY: 132e-12
MEMORY_DATA_IN_TO_BRAM_DATA_IN_DELAY: 132e-12
MEMORY_WEN_TO_BRAM_WEN_DELAY: 132e-12
MEMORY_REN_TO_BRAM_REN_DELAY: 132e-12
BRAM_DATA_OUT_TO_MEMORY_DATA_OUT_DELAY: 40e-12

88
openfpga_flow/openfpga_yosys_techlib/common/arith_map.v Normal file
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@ -0,0 +1,88 @@
// Copyright (C) 2020-2021 The SymbiFlow Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier:ISC
// module adder (
// input a,
// input b,
// input c_in,
// output c_out,
// output sum);
// assign {c_out, sum} = a + b + c_in;
// endmodule
//////////////////////////
// arithmetic //
//////////////////////////
(* techmap_celltype = "$alu" *)
module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
output [Y_WIDTH-1:0] CO;
//wire [1024:0] _TECHMAP_DO_ = "splitnets CARRY; clean";
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = B_buf;
wire [Y_WIDTH: 0 ] CARRY;
assign CO[Y_WIDTH-1:0] = CARRY[Y_WIDTH:1];
// Due to VPR limitations regarding IO connexion to carry chain,
// we generate the carry chain input signal using an intermediate adder
// since we can connect a & b from io pads, but not cin & cout
generate
adder intermediate_adder (
.cin ( ),
.cout (CARRY[0]),
.a (CI ),
.b (CI ),
.sumout ( )
);
adder first_adder (
.cin (CARRY[0]),
.cout (CARRY[1]),
.a (AA[0] ),
.b (BB[0] ),
.sumout (Y[0] )
);
endgenerate
genvar i;
generate for (i = 1; i < Y_WIDTH ; i = i+1) begin:gen3
adder my_adder (
.cin (CARRY[i] ),
.cout (CARRY[i+1]),
.a (AA[i] ),
.b (BB[i] ),
.sumout (Y[i] )
);
end endgenerate
assign X = AA ^ BB;
endmodule

9
openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v
View File

@ -1,3 +1,12 @@
module carry_adder (
input a, b, cin,
output sumout, cout
);
assign {cout, sumout} = a + b + cin;
endmodule
//----------------------------- //-----------------------------
// Dual-port RAM 128x8 bit (1Kbit) // Dual-port RAM 128x8 bit (1Kbit)
// Core logic // Core logic

2
openfpga_flow/scripts/run_fpga_flow.py
View File

@ -698,7 +698,7 @@ def run_rewrite_verilog():
# If there is a template script provided, replace parameters from configuration # If there is a template script provided, replace parameters from configuration
if not args.ys_rewrite_tmpl: if not args.ys_rewrite_tmpl:
script_cmd = [ script_cmd = [
"read_blif %s" % args.top_module+".blif", "read_blif -wideports %s" % args.top_module+".blif",
"write_verilog %s" % args.top_module+"_output_verilog.v" "write_verilog %s" % args.top_module+"_output_verilog.v"
] ]
command = [cad_tools["yosys_path"], "-p", "; ".join(script_cmd)] command = [cad_tools["yosys_path"], "-p", "; ".join(script_cmd)]

30
openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf
View File

@ -9,7 +9,7 @@
[GENERAL] [GENERAL]
run_engine=openfpga_shell run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = true power_analysis = false
spice_output=false spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 20*60 timeout_each_job = 20*60
@ -17,29 +17,37 @@ fpga_flow=yosys_vpr
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_vpr_device_layout= openfpga_vpr_device_layout=
openfpga_clock_modeling=ideal openfpga_clock_modeling=ideal
openfpga_fast_configuration= openfpga_fast_configuration=
yosys_adder_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/arith_map.v
[ARCHITECTURES] [ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml
[BENCHMARKS] [BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v # bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v # bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v
# bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v
[SYNTHESIS_PARAM] [SYNTHESIS_PARAM]
bench0_top = clock_divider bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys
bench0_top = adder_16
bench0_chan_width = 300 bench0_chan_width = 300
bench1_top = pulse_generator # bench0_top = clock_divider
bench1_chan_width = 300 # bench0_chan_width = 300
bench2_top = reset_generator # bench1_top = pulse_generator
bench2_chan_width = 300 # bench1_chan_width = 300
# bench2_top = reset_generator
# bench2_chan_width = 300
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test= end_flow_with_test=