diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v
index 2e7d31076..362d8f615 100644
--- a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v
+++ b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v
@@ -1,7 +1,7 @@
// Creating a scaleable adder
module adder_16(cout, sum, a, b, cin);
-parameter size = 6; /* declare a parameter. default required */
+parameter size = 3; /* declare a parameter. default required */
output cout;
output [size-1:0] sum; // sum uses the size parameter
input cin;
diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16_clk.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16_clk.v
new file mode 100644
index 000000000..e42f35414
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16_clk.v
@@ -0,0 +1,39 @@
+// Creating a scaleable adder
+
+module adder_16_clk #(
+ parameter size = 2
+)(
+ output reg cout,
+ output reg [size-1:0] sum, // sum uses the size parameter
+ input cin,
+ input [size-1:0] a, b, // 'a' and 'b' use the size parameter
+ input clk_in,
+ input rst
+);
+
+
+// reg [size-1:0] _sum;
+// reg _cout;
+
+always @(posedge clk_in) begin
+ if (rst)
+ {sum,cout} <= 0;
+ else
+ {sum,cout} <= a + b + cin;
+end
+
+// assign sum = _sum;
+// assign cout = _cout;
+
+// assign {cout, sum} = a + b + cin;
+
+endmodule
+
+
+
+
+
+
+
+
+
diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/wrapper.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/wrapper.v
new file mode 100644
index 000000000..8a54af192
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/wrapper.v
@@ -0,0 +1,41 @@
+module adder_16_wrapper(
+ output cout,
+ output sum_0,
+ output sum_1,
+ output sum_2,
+ output sum_3,
+ input cin,
+ input a_0,
+ input a_1,
+ input a_2,
+ input a_3,
+ input b_0,
+ input b_1,
+ input b_2,
+ input b_3
+);
+
+wire [4:0] sum;
+assign sum_0 = sum[0];
+assign sum_1 = sum[1];
+assign sum_2 = sum[2];
+assign sum_3 = sum[3];
+wire [4:0] a;
+assign a_0 = a[0];
+assign a_1 = a[1];
+assign a_2 = a[2];
+assign a_3 = a[3];
+wire [4:0] b;
+assign b_0 = b[0];
+assign b_1 = b[1];
+assign b_2 = b[2];
+assign b_3 = b[3];
+
+adder_16 DUT(
+ .cout(cout),
+ .sum(sum),
+ .cin(cin),
+ .a(a),
+ .b(b) );
+
+endmodule
\ No newline at end of file
diff --git a/openfpga_flow/misc/1k_bram.xml b/openfpga_flow/misc/1k_bram.xml
new file mode 100644
index 000000000..6b2713350
--- /dev/null
+++ b/openfpga_flow/misc/1k_bram.xml
@@ -0,0 +1,1177 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
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+
+
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+
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+
+
+
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+
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+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+ io_top.outpad io_top.inpad
+
+
+
+
+
+
+
+
+
+
+
+ io_right.outpad io_right.inpad
+
+
+
+
+
+
+
+
+
+
+
+ io_bottom.outpad io_bottom.inpad
+
+
+
+
+
+
+
+
+
+
+
+ io_left.outpad io_left.inpad
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ clb.clk clb.reset
+ clb.sc_in clb.cin clb.O[7:0] clb.I[8:0]
+ clb.O[15:8] clb.I[17:9]
+ clb.sc_out clb.cout
+
+
+
+
+
+
+
+
+
+
+
+
+
+ mult_18.a[0:5] mult_18.b[0:5] mult_18.out[0:11]
+ mult_18.a[6:11] mult_18.b[6:11] mult_18.out[12:23]
+ mult_18.a[12:17] mult_18.b[12:17] mult_18.out[24:35]
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ memory.clk
+
+ memory.waddr[2:0] memory.raddr[3:0] memory.data_in[3:0] memory.wen memory.data_out[3:0]
+ memory.waddr[6:3] memory.raddr[6:4] memory.data_in[7:4] memory.ren memory.data_out[7:4]
+
+
+
+
+
+
+
+
+
+ |
+ |
+
+
+
+
+
+
+
+
+
+
+
+ |
+ |
+
+
+
+
+
+
+ |
+
+
+
+ |
+ |
+
+
+
+
+
+
+ |
+
+
+
+ |
+ |
+
+
+
+
+
+
+ |
+
+
+
+ |
+ |
+
+
+
+
+
+
+ |
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1 1
+ 1
+
+
+
+ 1 1 1
+ 1 1
+
+
+
+ 1 1 1 1 1
+ 1 1 1 1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
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+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ ${LUT3_DELAY}
+ ${LUT3_DELAY}
+ ${LUT3_DELAY}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
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+
+
+
+
+
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+
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+
+
+
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+
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+
+
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+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ ${LUT4_DELAY}
+ ${LUT4_DELAY}
+ ${LUT4_DELAY}
+ ${LUT4_DELAY}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
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+
+
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+
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+
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+
+
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+
+
+
+
+
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+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
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+
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+
+
+
+
+
+
+
diff --git a/openfpga_flow/misc/1k_bram_openfpga.xml b/openfpga_flow/misc/1k_bram_openfpga.xml
new file mode 100644
index 000000000..0a9a1d65b
--- /dev/null
+++ b/openfpga_flow/misc/1k_bram_openfpga.xml
@@ -0,0 +1,352 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 10e-12
+
+
+ 10e-12
+
+
+
+
+
+
+
+
+ 10e-12
+
+
+ 10e-12
+
+
+
+
+
+
+
+
+ 10e-12
+
+
+ 10e-12
+
+
+
+
+
+
+
+
+ 10e-12
+
+
+ 10e-12
+
+
+
+
+
+
+
+
+
+
+
+ 10e-12 5e-12
+
+
+ 10e-12 5e-12
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
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+
+
+
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+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys
new file mode 100644
index 000000000..56c27123a
--- /dev/null
+++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys
@@ -0,0 +1,78 @@
+${READ_VERILOG_FILE}
+# read_verilog -lib cells_sim.v
+hierarchy -check -top ${TOP_MODULE}
+proc
+
+# flatten
+# tribuf -logic
+# deminout
+
+opt_expr
+opt_clean
+check
+opt
+wreduce
+peepopt
+opt_clean
+share
+# techmap -map +/cmp2lut.v -D LUT_WIDTH=4
+opt_expr
+opt_clean
+# ice40_dsp (if -dsp)
+alumacc
+opt
+fsm
+opt -fast
+memory -nomap
+opt_clean
+
+### BRAM
+# memory_bram -rules +/ice40/brams.txt
+# techmap -map +/ice40/brams_map.v
+# ice40_braminit
+
+### Map
+# opt -fast -mux_undef -undriven -fine
+# memory_map
+# opt -undriven -fine
+
+### map_gates
+# techmap -map +/techmap.v -map +/ice40/arith_map.v
+techmap -map ${YOSYS_ADDER_MAP_VERILOG}
+opt
+# abc -dff (only if -retime)
+# ice40_opt
+
+### map_ffs
+# dffsr2dff
+# dff2dffe -direct-match $_DFF_*
+# techmap -D NO_LUT -map +/ice40/cells_map.v
+# opt_expr -mux_undef
+# simplemap
+# ice40_ffinit
+# ice40_ffssr
+# ice40_opt -full
+stat
+### map_luts
+abc -lut ${LUT_SIZE}
+# abc (only if -abc2)
+# ice40_opt (only if -abc2)
+# techmap -map +/ice40/latches_map.v
+# simplemap (only if -noabc)
+# techmap -map +/gate2lut.v -D LUT_WIDTH=4 (only if -noabc)
+# abc -dress -lut 4 (skip if -noabc)
+# clean
+# ice40_unlut (only if -relut)
+# opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3 (only if -relut)
+
+### map_cells
+# techmap -map +/ice40/cells_map.v (with -D NO_LUT in vpr mode)
+# clean
+
+### check
+# hierarchy -check
+# stat
+# check -noinit
+### blif
+opt_clean -purge
+write_blif -conn -param ${OUTPUT_BLIF}
diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys
index 81b1e21ff..45c5fe758 100644
--- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys
+++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys
@@ -54,8 +54,6 @@ chtype -set $mul t:$__soft_mul# Extract arithmetic functions
#########################
# Run coarse synthesis
#########################
-# Run a tech map with default library
-techmap
alumacc
share
opt
@@ -66,6 +64,11 @@ opt -fast
memory -nomap
opt_clean
+#########################
+# Map $alu to carry chain
+#########################
+techmap -map ${YOSYS_ADDER_MAP_VERILOG}
+
#########################
# Map logics to BRAMs
#########################
@@ -92,6 +95,8 @@ opt_rmdff
opt_clean
opt
+stat
+
#########################
# Map LUTs
#########################
diff --git a/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga
index 0b5cfa232..e65745efd 100644
--- a/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga
@@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
-link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+link_openfpga_arch --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
diff --git a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_no_clk_modeling_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_no_clk_modeling_example_script.openfpga
index 506364e30..ffb290c12 100644
--- a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_no_clk_modeling_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_no_clk_modeling_example_script.openfpga
@@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
# Annotate the OpenFPGA architecture to VPR data base
# to debug use --verbose options
-link_openfpga_arch --sort_gsb_chan_node_in_edges
+link_openfpga_arch --activity_file and2_ace_out.act --sort_gsb_chan_node_in_edges
# Check and correct any naming conflicts in the BLIF netlist
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
diff --git a/openfpga_flow/openfpga_timing_annotation/design_variables.yml b/openfpga_flow/openfpga_timing_annotation/design_variables.yml
new file mode 100644
index 000000000..ca9d82179
--- /dev/null
+++ b/openfpga_flow/openfpga_timing_annotation/design_variables.yml
@@ -0,0 +1,70 @@
+L1_SB_MUX_DELAY: 1.44e-9
+L2_SB_MUX_DELAY: 1.44e-9
+L4_SB_MUX_DELAY: 1.44e-9
+CB_MUX_DELAY: 1.38e-9
+L1_WIRE_R: 100
+L1_WIRE_C: 1e-12
+L2_WIRE_R: 100
+L2_WIRE_C: 1e-12
+L4_WIRE_R: 100
+L4_WIRE_C: 1e-12
+INPAD_DELAY: 0.11e-9
+OUTPAD_DELAY: 0.11e-9
+FF_T_SETUP: 0.39e-9
+FF_T_CLK2Q: 0.43e-9
+LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
+LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
+LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
+FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
+LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
+FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
+LUT_CIN2LUT3_OUT_DELAY: 1.21e-9
+LUT_CIN2LUT4_OUT_DELAY: 1.21e-9
+LUT_CIN2COUT_DELAY: 1.21e-9
+LUT_IN2COUT_DELAY: 1.21e-9
+LUT3_DELAY: 0.92e-9
+LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
+LUT4_DELAY: 1.21e-9
+LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
+ADDER_LUT4_CIN2OUT_DELAY: 1.21e-9
+ADDER_LUT4_CIN2COUT_DELAY: 1.21e-9
+ADDER_LUT4_IN2OUT_DELAY: 1.21e-9
+ADDER_LUT4_IN2COUT_DELAY: 1.21e-9
+CLB_LR_IN2IN_DELAY: 1.46e-9
+CLB_LR_OUT2IN_DELAY: 1.46e-9
+MULT9_A2Y_DELAY_MAX: 1.523e-9
+MULT9_A2Y_DELAY_MIN: 0.776e-9
+MULT9_B2Y_DELAY_MAX: 1.523e-9
+MULT9_B2Y_DELAY_MIN: 0.776e-9
+MULT18_A2Y_DELAY_MAX: 1.523e-9
+MULT18_A2Y_DELAY_MIN: 0.776e-9
+MULT18_B2Y_DELAY_MAX: 1.523e-9
+MULT18_B2Y_DELAY_MIN: 0.776e-9
+MULT18_LR_A2A_DELAY_MAX: 1.46e-9
+MULT18_LR_A2A_DELAY_MIN: 1.46e-9
+MULT18_LR_B2B_DELAY_MAX: 1.46e-9
+MULT18_LR_B2B_DELAY_MIN: 1.46e-9
+
+
+################# BRAM Delays #################
+
+DPRAM_128x8_CLK_TO_WADDR_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_RADDR_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_DATA_IN_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_WEN_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_REN_DELAY: 509e-12
+DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 6.73e-9
+
+DPRAM_1024x8_CLK_TO_WADDR_DELAY: 509e-12
+DPRAM_1024x8_CLK_TO_RADDR_DELAY: 509e-12
+DPRAM_1024x8_CLK_TO_DATA_IN_DELAY: 509e-12
+DPRAM_1024x8_CLK_TO_WEN_DELAY: 509e-12
+DPRAM_1024x8_CLK_TO_REN_DELAY: 509e-12
+DPRAM_1024x8_CLK_TO_DATA_OUT_DELAY: 6.73e-9
+
+MEMORY_WADDR_TO_BRAM_WADDR_DELAY: 132e-12
+MEMORY_RADDR_TO_BRAM_RADDR_DELAY: 132e-12
+MEMORY_DATA_IN_TO_BRAM_DATA_IN_DELAY: 132e-12
+MEMORY_WEN_TO_BRAM_WEN_DELAY: 132e-12
+MEMORY_REN_TO_BRAM_REN_DELAY: 132e-12
+BRAM_DATA_OUT_TO_MEMORY_DATA_OUT_DELAY: 40e-12
\ No newline at end of file
diff --git a/openfpga_flow/openfpga_yosys_techlib/common/arith_map.v b/openfpga_flow/openfpga_yosys_techlib/common/arith_map.v
new file mode 100644
index 000000000..03f873b4b
--- /dev/null
+++ b/openfpga_flow/openfpga_yosys_techlib/common/arith_map.v
@@ -0,0 +1,88 @@
+// Copyright (C) 2020-2021 The SymbiFlow Authors.
+//
+// Use of this source code is governed by a ISC-style
+// license that can be found in the LICENSE file or at
+// https://opensource.org/licenses/ISC
+//
+// SPDX-License-Identifier:ISC
+
+
+// module adder (
+// input a,
+// input b,
+// input c_in,
+// output c_out,
+// output sum);
+
+// assign {c_out, sum} = a + b + c_in;
+
+// endmodule
+
+
+//////////////////////////
+// arithmetic //
+//////////////////////////
+
+(* techmap_celltype = "$alu" *)
+module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO);
+
+ parameter A_SIGNED = 0;
+ parameter B_SIGNED = 0;
+ parameter A_WIDTH = 1;
+ parameter B_WIDTH = 1;
+ parameter Y_WIDTH = 1;
+
+ input [A_WIDTH-1:0] A;
+ input [B_WIDTH-1:0] B;
+ output [Y_WIDTH-1:0] X, Y;
+
+ input CI, BI;
+ output [Y_WIDTH-1:0] CO;
+
+ //wire [1024:0] _TECHMAP_DO_ = "splitnets CARRY; clean";
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] A_buf, B_buf;
+ \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+ \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] AA = A_buf;
+ (* force_downto *)
+ wire [Y_WIDTH-1:0] BB = B_buf;
+ wire [Y_WIDTH: 0 ] CARRY;
+
+ assign CO[Y_WIDTH-1:0] = CARRY[Y_WIDTH:1];
+ // Due to VPR limitations regarding IO connexion to carry chain,
+ // we generate the carry chain input signal using an intermediate adder
+ // since we can connect a & b from io pads, but not cin & cout
+ generate
+ adder intermediate_adder (
+ .cin ( ),
+ .cout (CARRY[0]),
+ .a (CI ),
+ .b (CI ),
+ .sumout ( )
+ );
+
+ adder first_adder (
+ .cin (CARRY[0]),
+ .cout (CARRY[1]),
+ .a (AA[0] ),
+ .b (BB[0] ),
+ .sumout (Y[0] )
+ );
+ endgenerate
+
+ genvar i;
+ generate for (i = 1; i < Y_WIDTH ; i = i+1) begin:gen3
+ adder my_adder (
+ .cin (CARRY[i] ),
+ .cout (CARRY[i+1]),
+ .a (AA[i] ),
+ .b (BB[i] ),
+ .sumout (Y[i] )
+ );
+ end endgenerate
+ assign X = AA ^ BB;
+endmodule
diff --git a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v
index 9a5dfd26e..bc54335ac 100644
--- a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v
+++ b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v
@@ -1,3 +1,12 @@
+module carry_adder (
+ input a, b, cin,
+ output sumout, cout
+);
+
+ assign {cout, sumout} = a + b + cin;
+
+endmodule
+
//-----------------------------
// Dual-port RAM 128x8 bit (1Kbit)
// Core logic
diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py
index a333ebb8f..f74514e3c 100644
--- a/openfpga_flow/scripts/run_fpga_flow.py
+++ b/openfpga_flow/scripts/run_fpga_flow.py
@@ -698,7 +698,7 @@ def run_rewrite_verilog():
# If there is a template script provided, replace parameters from configuration
if not args.ys_rewrite_tmpl:
script_cmd = [
- "read_blif %s" % args.top_module+".blif",
+ "read_blif -wideports %s" % args.top_module+".blif",
"write_verilog %s" % args.top_module+"_output_verilog.v"
]
command = [cad_tools["yosys_path"], "-p", "; ".join(script_cmd)]
diff --git a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf
index f246a8cf1..0b8fde8fa 100644
--- a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf
+++ b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf
@@ -9,7 +9,7 @@
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
-power_analysis = true
+power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 20*60
@@ -17,29 +17,37 @@ fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
-openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_vpr_device_layout=
openfpga_clock_modeling=ideal
openfpga_fast_configuration=
+yosys_adder_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/arith_map.v
+
[ARCHITECTURES]
-arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml
[BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v
-bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v
-bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v
+# bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v
+# bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v
+# bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v
[SYNTHESIS_PARAM]
-bench0_top = clock_divider
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys
+
+bench0_top = adder_16
bench0_chan_width = 300
-bench1_top = pulse_generator
-bench1_chan_width = 300
+# bench0_top = clock_divider
+# bench0_chan_width = 300
-bench2_top = reset_generator
-bench2_chan_width = 300
+# bench1_top = pulse_generator
+# bench1_chan_width = 300
+
+# bench2_top = reset_generator
+# bench2_chan_width = 300
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=