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Merge pull request #14 from LNIS-Projects/dev 

Dev - Critical bug fixing and add support for MUX2 standard cell mapping
This commit is contained in:
egiacomin 2019-07-17 11:55:52 -06:00 committed by GitHub
parent 4672311aae 32e3a556b9
commit 77e1480a4c
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GPG Key ID: 4AEE18F83AFDEB23
9 changed files with 157 additions and 45 deletions
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1
fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml
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@ -269,6 +269,7 @@
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INVTX1"/>
<output_buffer exist="on" circuit_model_name="INVTX1"/>
<lut_input_inverter exist="on" circuit_model_name="INVTX1"/>
<lut_input_buffer exist="on" circuit_model_name="buf4"/>
<pass_gate_logic circuit_model_name="TGATE"/>
<port type="input" prefix="in" size="6"/>

3
vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h
View File

@ -55,7 +55,8 @@ enum e_spice_model_pass_gate_logic_type {
enum e_spice_model_gate_type {
SPICE_MODEL_GATE_AND,
SPICE_MODEL_GATE_OR
SPICE_MODEL_GATE_OR,
SPICE_MODEL_GATE_MUX2
};
/* Transistor-level basic informations*/

4
vpr7_x2p/libarchfpga/SRC/read_xml_spice.c
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@ -616,8 +616,10 @@ static void ProcessSpiceModelGate(ezxml_t Node,
gate_info->type = SPICE_MODEL_GATE_AND;
} else if (0 == strcmp(FindProperty(Node,"topology",TRUE),"OR")) {
gate_info->type = SPICE_MODEL_GATE_OR;
} else if (0 == strcmp(FindProperty(Node,"topology",TRUE),"MUX2")) {
gate_info->type = SPICE_MODEL_GATE_MUX2;
} else {
vpr_printf(TIO_MESSAGE_ERROR,"[LINE %d] Invalid topology of gates. Should be [AND|OR].\n",
vpr_printf(TIO_MESSAGE_ERROR,"[LINE %d] Invalid topology of gates. Should be [AND|OR|MUX2].\n",
Node->line);
exit(1);
}

8
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c
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@ -440,7 +440,15 @@ void config_spice_model_input_output_buffers_pass_gate(int num_spice_models,
exit(1);
}
/* Copy the information from found spice model to current spice model*/
/* copy gate info if this is a standard cell */
if (SPICE_MODEL_GATE == pgl_spice_model->type) {
assert ( SPICE_MODEL_GATE_MUX2 == pgl_spice_model->design_tech_info.gate_info->type);
spice_model[i].design_tech_info.gate_info = (t_spice_model_gate*)my_calloc(1, sizeof(t_spice_model_gate));
memcpy(spice_model[i].design_tech_info.gate_info, pgl_spice_model->design_tech_info.gate_info, sizeof(t_spice_model_gate));
} else {
assert (SPICE_MODEL_PASSGATE == pgl_spice_model->type);
memcpy(spice_model[i].pass_gate_logic, pgl_spice_model->design_tech_info.pass_gate_info, sizeof(t_spice_model_pass_gate_logic));
}
/* Recover the spice_model_name */
spice_model[i].pass_gate_logic->spice_model_name = my_strdup(pgl_spice_model->name);
spice_model[i].pass_gate_logic->spice_model = pgl_spice_model;

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
View File

@ -3213,7 +3213,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
cur_num_sram,
cur_num_sram + num_mux_conf_bits - 1);
fprintf(fp, "is_explicit_mappingf\n");
fprintf(fp, "`endif\n");
/* Call the MUX SPICE model */

91
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c
View File

@ -1104,6 +1104,19 @@ void dump_verilog_mux_basis_module(FILE* fp,
spice_mux_model->spice_mux_arch,
spice_mux_model->size);
/* Exception: if tgate is a standard cell, we skip the basis circuit generation */
t_spice_model* tgate_spice_model = spice_mux_model->spice_model->pass_gate_logic->spice_model;
if (SPICE_MODEL_GATE == tgate_spice_model->type) {
assert (SPICE_MODEL_GATE_MUX2 == tgate_spice_model->design_tech_info.gate_info->type);
/* Double check the mux structure, which should be tree-like */
if ( SPICE_MODEL_STRUCTURE_TREE != spice_mux_model->spice_mux_arch->structure ) {
vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Structure of Circuit model (%s) should be tree-like because it is linked to a 2:1 MUX!\n",
__FILE__, __LINE__, spice_mux_model->spice_model->name);
exit(1);
}
return;
}
/* Corner case: Error out MUX_SIZE = 2, automatcially give a one-level structure */
/*
if ((2 == spice_mux_model->size)&&(SPICE_MODEL_STRUCTURE_ONELEVEL != spice_mux_model->spice_model->design_tech_info.structure)) {
@ -1115,9 +1128,9 @@ void dump_verilog_mux_basis_module(FILE* fp,
/* Prepare the basis subckt name:
*/
mux_basis_subckt_name = generate_verilog_mux_subckt_name(spice_mux_model->spice_model, spice_mux_model->size, verilog_mux_basis_posfix);
mux_basis_subckt_name = generate_verilog_mux_basis_subckt_name(spice_mux_model->spice_model, spice_mux_model->size, verilog_mux_basis_posfix);
special_basis_subckt_name = generate_verilog_mux_subckt_name(spice_mux_model->spice_model, spice_mux_model->size, verilog_mux_special_basis_posfix);
special_basis_subckt_name = generate_verilog_mux_basis_subckt_name(spice_mux_model->spice_model, spice_mux_model->size, verilog_mux_special_basis_posfix);
/* deteremine the number of inputs of basis subckt */
num_input_basis_subckt = spice_mux_model->spice_mux_arch->num_input_basis;
@ -1228,6 +1241,71 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp,
out_idx = j/2;
/* Each basis mux2to1: <given_name> <input0> <input1> <output> <sram> <sram_inv> svdd sgnd <subckt_name> */
fprintf(fp, "%s mux_basis_no%d (", mux_basis_subckt_name, mux_basis_cnt); /* given_name */
/* For MUX2 standard cell */
t_spice_model* tgate_spice_model = spice_model.pass_gate_logic->spice_model;
/* For non-standard cells */
if (SPICE_MODEL_GATE == tgate_spice_model->type) {
assert(SPICE_MODEL_GATE_MUX2 == tgate_spice_model->design_tech_info.gate_info->type);
int num_input_port = 0;
int num_output_port = 0;
t_spice_model_port** input_port = NULL;
t_spice_model_port** output_port = NULL;
input_port = find_spice_model_ports(tgate_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE);
output_port = find_spice_model_ports(tgate_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE);
/* Quick check on the number of ports */
assert(3 == num_input_port); /* A, B and SEL */
assert(1 == num_output_port); /* OUT */
bool use_explicit_port_map;
if ( (true == is_explicit_mapping)
|| (TRUE == tgate_spice_model->dump_explicit_port_map) ) {
use_explicit_port_map = true;
}
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, tgate_spice_model, FALSE, FALSE, my_bool_to_boolean(use_explicit_port_map))) {
fprintf(fp, ",\n");
}
if (true == use_explicit_port_map) {
fprintf(fp, ".%s(", input_port[0]->lib_name);
}
/* For intermediate buffers */
if (TRUE == inter_buf_loc[level]) {
fprintf(fp, "mux2_l%d_in_buf[%d]", level, j); /* input0 */
} else {
fprintf(fp, "mux2_l%d_in[%d]", level, j); /* input0 */
}
if (true == use_explicit_port_map) {
fprintf(fp, "), .%s(", input_port[1]->lib_name);
} else {
fprintf(fp, ", ");
}
/* For intermediate buffers */
if (TRUE == inter_buf_loc[level]) {
fprintf(fp, "mux2_l%d_in_buf[%d]", level, nextj); /* input1 */
} else {
fprintf(fp, "mux2_l%d_in[%d]", level, nextj); /* input1 */
}
if (true == use_explicit_port_map) {
fprintf(fp, "), .%s(", output_port[0]->lib_name);
} else {
fprintf(fp, ", ");
}
fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */
if (true == use_explicit_port_map) {
fprintf(fp, "), .%s(", input_port[2]->lib_name);
} else {
fprintf(fp, ", ");
}
fprintf(fp, "%s[%d]", sram_port[0]->prefix, i); /* sram */
if (true == use_explicit_port_map) {
fprintf(fp, "));\n");
} else {
fprintf(fp, ");\n");
}
} else {
assert (SPICE_MODEL_PASSGATE == tgate_spice_model->type);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
@ -1264,6 +1342,7 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp,
} else {
fprintf(fp, ");\n");
}
}
/* For intermediate buffers */
if (TRUE == inter_buf_loc[nextlevel]) {
/* Find the input port, output port, and sram port*/
@ -1568,9 +1647,9 @@ void dump_verilog_cmos_mux_submodule(FILE* fp,
char* mux_basis_subckt_name = NULL;
char* mux_special_basis_subckt_name = NULL;
mux_basis_subckt_name = generate_verilog_mux_subckt_name(&spice_model, mux_size, verilog_mux_basis_posfix);
mux_basis_subckt_name = generate_verilog_mux_basis_subckt_name(&spice_model, mux_size, verilog_mux_basis_posfix);
mux_special_basis_subckt_name = generate_verilog_mux_subckt_name(&spice_model, mux_size, verilog_mux_special_basis_posfix);
mux_special_basis_subckt_name = generate_verilog_mux_basis_subckt_name(&spice_model, mux_size, verilog_mux_special_basis_posfix);
/* Make sure we have a valid file handler*/
if (NULL == fp) {
@ -2077,9 +2156,9 @@ void dump_verilog_rram_mux_submodule(FILE* fp,
char* mux_basis_subckt_name = NULL;
char* mux_special_basis_subckt_name = NULL;
mux_basis_subckt_name = generate_verilog_mux_subckt_name(&spice_model, mux_size, verilog_mux_basis_posfix);
mux_basis_subckt_name = generate_verilog_mux_basis_subckt_name(&spice_model, mux_size, verilog_mux_basis_posfix);
mux_special_basis_subckt_name = generate_verilog_mux_subckt_name(&spice_model, mux_size, verilog_mux_special_basis_posfix);
mux_special_basis_subckt_name = generate_verilog_mux_basis_subckt_name(&spice_model, mux_size, verilog_mux_special_basis_posfix);
/* Make sure we have a valid file handler*/
if (NULL == fp) {

18
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c
View File

@ -2915,6 +2915,24 @@ char* generate_verilog_mem_subckt_name(t_spice_model* spice_model,
return subckt_name;
}
/* Generate the subckt name for a MUX module/submodule */
char* generate_verilog_mux_basis_subckt_name(t_spice_model* spice_model,
int mux_size, char* postfix) {
char* mux_subckt_name = NULL;
/* If the tgate spice model of this MUX is a MUX2 standard cell,
* the mux_subckt name will be the name of the standard cell
*/
if ( SPICE_MODEL_GATE == spice_model->pass_gate_logic->spice_model->type) {
assert ( SPICE_MODEL_GATE_MUX2 == spice_model->design_tech_info.gate_info->type);
mux_subckt_name = my_strdup(spice_model->pass_gate_logic->spice_model->name);
} else {
mux_subckt_name = generate_verilog_mux_subckt_name(spice_model, mux_size, postfix);
}
return mux_subckt_name;
}
/* Generate the subckt name for a MUX module/submodule */
char* generate_verilog_mux_subckt_name(t_spice_model* spice_model,

3
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h
View File

@ -221,6 +221,9 @@ char* generate_verilog_mem_subckt_name(t_spice_model* spice_model,
t_spice_model* mem_model,
char* postfix);
char* generate_verilog_mux_basis_subckt_name(t_spice_model* spice_model,
int mux_size, char* postfix);
char* generate_verilog_mux_subckt_name(t_spice_model* spice_model,
int mux_size, char* postfix);

2
vpr7_x2p/vpr/regression_verilog.sh
View File

@ -33,7 +33,7 @@ perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path
cd -
# Run VPR
#echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping"
echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping"
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping
cd $fpga_flow_scripts