From 6e1d49d74e2c03cd049a96dc66149ee912b603ad Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Jul 2019 07:54:23 -0600 Subject: [PATCH 1/5] start to support direct mapping to MUX2 standard cells --- .../fpga_spice/k6_N10_sram_tsmc40nm_TT.xml | 1 + .../SRC/fpga_spice_include/spice_types.h | 3 +- vpr7_x2p/libarchfpga/SRC/read_xml_spice.c | 4 +- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 136 +++++++++++++----- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 15 +- vpr7_x2p/vpr/regression_verilog.sh | 2 +- 6 files changed, 120 insertions(+), 41 deletions(-) diff --git a/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml b/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml index f54bab155..5b0b85ae7 100755 --- a/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml +++ b/fpga_flow/arch/fpga_spice/k6_N10_sram_tsmc40nm_TT.xml @@ -269,6 +269,7 @@ + diff --git a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h index e99869c93..76b58c744 100644 --- a/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h +++ b/vpr7_x2p/libarchfpga/SRC/fpga_spice_include/spice_types.h @@ -55,7 +55,8 @@ enum e_spice_model_pass_gate_logic_type { enum e_spice_model_gate_type { SPICE_MODEL_GATE_AND, - SPICE_MODEL_GATE_OR + SPICE_MODEL_GATE_OR, + SPICE_MODEL_GATE_MUX2 }; /* Transistor-level basic informations*/ diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c index 9e3a511bf..c0a79aa23 100644 --- a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c +++ b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c @@ -616,8 +616,10 @@ static void ProcessSpiceModelGate(ezxml_t Node, gate_info->type = SPICE_MODEL_GATE_AND; } else if (0 == strcmp(FindProperty(Node,"topology",TRUE),"OR")) { gate_info->type = SPICE_MODEL_GATE_OR; + } else if (0 == strcmp(FindProperty(Node,"topology",TRUE),"MUX2")) { + gate_info->type = SPICE_MODEL_GATE_MUX2; } else { - vpr_printf(TIO_MESSAGE_ERROR,"[LINE %d] Invalid topology of gates. Should be [AND|OR].\n", + vpr_printf(TIO_MESSAGE_ERROR,"[LINE %d] Invalid topology of gates. Should be [AND|OR|MUX2].\n", Node->line); exit(1); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 79a794729..61012c6fb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -1104,6 +1104,19 @@ void dump_verilog_mux_basis_module(FILE* fp, spice_mux_model->spice_mux_arch, spice_mux_model->size); + /* Exception: if tgate is a standard cell, we skip the basis circuit generation */ + t_spice_model* tgate_spice_model = spice_mux_model->spice_model->pass_gate_logic->spice_model; + if (SPICE_MODEL_GATE == tgate_spice_model->type) { + assert (SPICE_MODEL_GATE_MUX2 == tgate_spice_model->design_tech_info.gate_info->type); + /* Double check the mux structure, which should be tree-like */ + if ( SPICE_MODEL_STRUCTURE_TREE != spice_mux_model->spice_mux_arch->structure ) { + vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Structure of Circuit model (%s) should be tree-like because it is linked to a 2:1 MUX!\n", + __FILE__, __LINE__, spice_mux_model->spice_model->name); + exit(1); + } + return; + } + /* Corner case: Error out MUX_SIZE = 2, automatcially give a one-level structure */ /* if ((2 == spice_mux_model->size)&&(SPICE_MODEL_STRUCTURE_ONELEVEL != spice_mux_model->spice_model->design_tech_info.structure)) { @@ -1228,41 +1241,96 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, out_idx = j/2; /* Each basis mux2to1: svdd sgnd */ fprintf(fp, "%s mux_basis_no%d (", mux_basis_subckt_name, mux_basis_cnt); /* given_name */ - /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { - fprintf(fp, ",\n"); - } - if (true == is_explicit_mapping) { - fprintf(fp, ".in("); - } - /* For intermediate buffers */ - if (TRUE == inter_buf_loc[level]) { - fprintf(fp, "mux2_l%d_in_buf[%d:%d]", level, j, nextj); /* input0 input1 */ + /* For MUX2 standard cell */ + t_spice_model* tgate_spice_model = spice_model.pass_gate_logic->spice_model; + /* For non-standard cells */ + if (SPICE_MODEL_GATE == tgate_spice_model->type) { + assert(SPICE_MODEL_GATE_MUX2 == tgate_spice_model->design_tech_info.gate_info->type); + int num_input_port = 0; + int num_output_port = 0; + t_spice_model_port** input_port = NULL; + t_spice_model_port** output_port = NULL; + /* Quick check on the number of ports */ + assert(3 == num_input_port); /* A, B and SEL */ + assert(1 == num_output_port); /* OUT */ + + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, tgate_spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + fprintf(fp, ",\n"); + } + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", input_port[0]->lib_name); + } + /* For intermediate buffers */ + if (TRUE == inter_buf_loc[level]) { + fprintf(fp, "mux2_l%d_in_buf[%d]", level, j); /* input0 */ + } else { + fprintf(fp, "mux2_l%d_in[%d]", level, j); /* input0 */ + } + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", input_port[1]->lib_name); + } + /* For intermediate buffers */ + if (TRUE == inter_buf_loc[level]) { + fprintf(fp, "mux2_l%d_in_buf[%d]", level, nextj); /* input1 */ + } else { + fprintf(fp, "mux2_l%d_in[%d]", level, nextj); /* input1 */ + } + if (true == is_explicit_mapping) { + fprintf(fp, "), .%s(", output_port[0]->lib_name); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .%s(", input_port[2]->lib_name); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s[%d]", sram_port[0]->prefix, i); /* sram */ + if (true == is_explicit_mapping) { + fprintf(fp, "));\n"); + } else { + fprintf(fp, ");\n"); + } } else { - fprintf(fp, "mux2_l%d_in[%d:%d]", level, j, nextj); /* input0 input1 */ - } - if (true == is_explicit_mapping) { - fprintf(fp, "), .out("); - } else { - fprintf(fp, ", "); - } - fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */ - if (true == is_explicit_mapping) { - fprintf(fp, "), .mem("); - } else { - fprintf(fp, ", "); - } - fprintf(fp, "%s[%d]", sram_port[0]->prefix, i); /* sram */ - if (true == is_explicit_mapping) { - fprintf(fp, "), .mem_inv("); - } else { - fprintf(fp, ", "); - } - fprintf(fp, "%s_inv[%d]", sram_port[0]->prefix, i); /* sram_inv */ - if (true == is_explicit_mapping) { - fprintf(fp, "));\n"); - } else { - fprintf(fp, ");\n"); + assert (SPICE_MODEL_PASSGATE == tgate_spice_model->type); + /* Dump global ports */ + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + fprintf(fp, ",\n"); + } + if (true == is_explicit_mapping) { + fprintf(fp, ".in("); + } + /* For intermediate buffers */ + if (TRUE == inter_buf_loc[level]) { + fprintf(fp, "mux2_l%d_in_buf[%d:%d]", level, j, nextj); /* input0 input1 */ + } else { + fprintf(fp, "mux2_l%d_in[%d:%d]", level, j, nextj); /* input0 input1 */ + } + if (true == is_explicit_mapping) { + fprintf(fp, "), .out("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s[%d]", sram_port[0]->prefix, i); /* sram */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem_inv("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s_inv[%d]", sram_port[0]->prefix, i); /* sram_inv */ + if (true == is_explicit_mapping) { + fprintf(fp, "));\n"); + } else { + fprintf(fp, ");\n"); + } } /* For intermediate buffers */ if (TRUE == inter_buf_loc[nextlevel]) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 67a31e10f..beaaebac5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -2921,10 +2921,17 @@ char* generate_verilog_mux_subckt_name(t_spice_model* spice_model, int mux_size, char* postfix) { char* mux_subckt_name = NULL; - mux_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model->name) + 5 - + strlen(my_itoa(mux_size)) + strlen(postfix) + 1)); - sprintf(mux_subckt_name, "%s_size%d%s", - spice_model->name, mux_size, postfix); + /* If the tgate spice model of this MUX is a MUX2 standard cell, + * the mux_subckt name will be the name of the standard cell + */ + if ( SPICE_MODEL_GATE_MUX2 == spice_model->pass_gate_logic->spice_model->type) { + mux_subckt_name = my_strdup(spice_model->pass_gate_logic->spice_model->name); + } else { + mux_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model->name) + 5 + + strlen(my_itoa(mux_size)) + strlen(postfix) + 1)); + sprintf(mux_subckt_name, "%s_size%d%s", + spice_model->name, mux_size, postfix); + } return mux_subckt_name; } diff --git a/vpr7_x2p/vpr/regression_verilog.sh b/vpr7_x2p/vpr/regression_verilog.sh index 644c9c3f3..47608013f 100755 --- a/vpr7_x2p/vpr/regression_verilog.sh +++ b/vpr7_x2p/vpr/regression_verilog.sh @@ -33,7 +33,7 @@ perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path cd - # Run VPR -#echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping" +echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping" ./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping cd $fpga_flow_scripts From dcc96bf7f5bc8af0fd63fafa4814fbfe12435491 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Jul 2019 08:25:52 -0600 Subject: [PATCH 2/5] bug fixing --- vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c | 10 +++++++++- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c | 7 ++++++- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 3 ++- 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c index 5212a83ee..7304a25b6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c @@ -440,7 +440,15 @@ void config_spice_model_input_output_buffers_pass_gate(int num_spice_models, exit(1); } /* Copy the information from found spice model to current spice model*/ - memcpy(spice_model[i].pass_gate_logic, pgl_spice_model->design_tech_info.pass_gate_info, sizeof(t_spice_model_pass_gate_logic)); + /* copy gate info if this is a standard cell */ + if (SPICE_MODEL_GATE == pgl_spice_model->type) { + assert ( SPICE_MODEL_GATE_MUX2 == pgl_spice_model->design_tech_info.gate_info->type); + spice_model[i].design_tech_info.gate_info = (t_spice_model_gate*)my_calloc(1, sizeof(t_spice_model_gate)); + memcpy(spice_model[i].design_tech_info.gate_info, pgl_spice_model->design_tech_info.gate_info, sizeof(t_spice_model_gate)); + } else { + assert (SPICE_MODEL_PASSGATE == pgl_spice_model->type); + memcpy(spice_model[i].pass_gate_logic, pgl_spice_model->design_tech_info.pass_gate_info, sizeof(t_spice_model_pass_gate_logic)); + } /* Recover the spice_model_name */ spice_model[i].pass_gate_logic->spice_model_name = my_strdup(pgl_spice_model->name); spice_model[i].pass_gate_logic->spice_model = pgl_spice_model; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 61012c6fb..83e87ecd5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -1250,6 +1250,9 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, int num_output_port = 0; t_spice_model_port** input_port = NULL; t_spice_model_port** output_port = NULL; + + input_port = find_spice_model_ports(tgate_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE); + output_port = find_spice_model_ports(tgate_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE); /* Quick check on the number of ports */ assert(3 == num_input_port); /* A, B and SEL */ assert(1 == num_output_port); /* OUT */ @@ -1268,7 +1271,9 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, fprintf(fp, "mux2_l%d_in[%d]", level, j); /* input0 */ } if (true == is_explicit_mapping) { - fprintf(fp, ".%s(", input_port[1]->lib_name); + fprintf(fp, "), .%s(", input_port[1]->lib_name); + } else { + fprintf(fp, ", "); } /* For intermediate buffers */ if (TRUE == inter_buf_loc[level]) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index beaaebac5..0aba462d8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -2924,7 +2924,8 @@ char* generate_verilog_mux_subckt_name(t_spice_model* spice_model, /* If the tgate spice model of this MUX is a MUX2 standard cell, * the mux_subckt name will be the name of the standard cell */ - if ( SPICE_MODEL_GATE_MUX2 == spice_model->pass_gate_logic->spice_model->type) { + if ( SPICE_MODEL_GATE == spice_model->pass_gate_logic->spice_model->type) { + assert ( SPICE_MODEL_GATE_MUX2 == spice_model->design_tech_info.gate_info->type); mux_subckt_name = my_strdup(spice_model->pass_gate_logic->spice_model->name); } else { mux_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model->name) + 5 From a2505ff16ad4a34f908dd488ba2246a2c1ceba97 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Jul 2019 08:36:09 -0600 Subject: [PATCH 3/5] turn on std cell explicit port map --- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 83e87ecd5..a0b0f3c25 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -1256,12 +1256,18 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, /* Quick check on the number of ports */ assert(3 == num_input_port); /* A, B and SEL */ assert(1 == num_output_port); /* OUT */ + + bool use_explicit_port_map; + if ( (true == is_explicit_mapping) + || (TRUE == tgate_spice_model->dump_explicit_port_map) ) { + use_explicit_port_map = true; + } /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, tgate_spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, tgate_spice_model, FALSE, FALSE, my_bool_to_boolean(use_explicit_port_map))) { fprintf(fp, ",\n"); } - if (true == is_explicit_mapping) { + if (true == use_explicit_port_map) { fprintf(fp, ".%s(", input_port[0]->lib_name); } /* For intermediate buffers */ @@ -1270,7 +1276,7 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, } else { fprintf(fp, "mux2_l%d_in[%d]", level, j); /* input0 */ } - if (true == is_explicit_mapping) { + if (true == use_explicit_port_map) { fprintf(fp, "), .%s(", input_port[1]->lib_name); } else { fprintf(fp, ", "); @@ -1281,19 +1287,19 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, } else { fprintf(fp, "mux2_l%d_in[%d]", level, nextj); /* input1 */ } - if (true == is_explicit_mapping) { + if (true == use_explicit_port_map) { fprintf(fp, "), .%s(", output_port[0]->lib_name); } else { fprintf(fp, ", "); } fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */ - if (true == is_explicit_mapping) { + if (true == use_explicit_port_map) { fprintf(fp, "), .%s(", input_port[2]->lib_name); } else { fprintf(fp, ", "); } fprintf(fp, "%s[%d]", sram_port[0]->prefix, i); /* sram */ - if (true == is_explicit_mapping) { + if (true == use_explicit_port_map) { fprintf(fp, "));\n"); } else { fprintf(fp, ");\n"); From 8b8e18a8de14a54ca62961d02008b894e9bf137d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Jul 2019 08:59:57 -0600 Subject: [PATCH 4/5] bug fixing for mux subckt names --- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 12 +++++----- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 24 +++++++++++++------ .../vpr/SRC/fpga_x2p/verilog/verilog_utils.h | 3 +++ 3 files changed, 26 insertions(+), 13 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index a0b0f3c25..c66c00f67 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -1128,9 +1128,9 @@ void dump_verilog_mux_basis_module(FILE* fp, /* Prepare the basis subckt name: */ - mux_basis_subckt_name = generate_verilog_mux_subckt_name(spice_mux_model->spice_model, spice_mux_model->size, verilog_mux_basis_posfix); + mux_basis_subckt_name = generate_verilog_mux_basis_subckt_name(spice_mux_model->spice_model, spice_mux_model->size, verilog_mux_basis_posfix); - special_basis_subckt_name = generate_verilog_mux_subckt_name(spice_mux_model->spice_model, spice_mux_model->size, verilog_mux_special_basis_posfix); + special_basis_subckt_name = generate_verilog_mux_basis_subckt_name(spice_mux_model->spice_model, spice_mux_model->size, verilog_mux_special_basis_posfix); /* deteremine the number of inputs of basis subckt */ num_input_basis_subckt = spice_mux_model->spice_mux_arch->num_input_basis; @@ -1647,9 +1647,9 @@ void dump_verilog_cmos_mux_submodule(FILE* fp, char* mux_basis_subckt_name = NULL; char* mux_special_basis_subckt_name = NULL; - mux_basis_subckt_name = generate_verilog_mux_subckt_name(&spice_model, mux_size, verilog_mux_basis_posfix); + mux_basis_subckt_name = generate_verilog_mux_basis_subckt_name(&spice_model, mux_size, verilog_mux_basis_posfix); - mux_special_basis_subckt_name = generate_verilog_mux_subckt_name(&spice_model, mux_size, verilog_mux_special_basis_posfix); + mux_special_basis_subckt_name = generate_verilog_mux_basis_subckt_name(&spice_model, mux_size, verilog_mux_special_basis_posfix); /* Make sure we have a valid file handler*/ if (NULL == fp) { @@ -2156,9 +2156,9 @@ void dump_verilog_rram_mux_submodule(FILE* fp, char* mux_basis_subckt_name = NULL; char* mux_special_basis_subckt_name = NULL; - mux_basis_subckt_name = generate_verilog_mux_subckt_name(&spice_model, mux_size, verilog_mux_basis_posfix); + mux_basis_subckt_name = generate_verilog_mux_basis_subckt_name(&spice_model, mux_size, verilog_mux_basis_posfix); - mux_special_basis_subckt_name = generate_verilog_mux_subckt_name(&spice_model, mux_size, verilog_mux_special_basis_posfix); + mux_special_basis_subckt_name = generate_verilog_mux_basis_subckt_name(&spice_model, mux_size, verilog_mux_special_basis_posfix); /* Make sure we have a valid file handler*/ if (NULL == fp) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 0aba462d8..f280af78d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -2915,10 +2915,9 @@ char* generate_verilog_mem_subckt_name(t_spice_model* spice_model, return subckt_name; } - /* Generate the subckt name for a MUX module/submodule */ -char* generate_verilog_mux_subckt_name(t_spice_model* spice_model, - int mux_size, char* postfix) { +char* generate_verilog_mux_basis_subckt_name(t_spice_model* spice_model, + int mux_size, char* postfix) { char* mux_subckt_name = NULL; /* If the tgate spice model of this MUX is a MUX2 standard cell, @@ -2928,15 +2927,26 @@ char* generate_verilog_mux_subckt_name(t_spice_model* spice_model, assert ( SPICE_MODEL_GATE_MUX2 == spice_model->design_tech_info.gate_info->type); mux_subckt_name = my_strdup(spice_model->pass_gate_logic->spice_model->name); } else { - mux_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model->name) + 5 - + strlen(my_itoa(mux_size)) + strlen(postfix) + 1)); - sprintf(mux_subckt_name, "%s_size%d%s", - spice_model->name, mux_size, postfix); + mux_subckt_name = generate_verilog_mux_subckt_name(spice_model, mux_size, postfix); } return mux_subckt_name; } + +/* Generate the subckt name for a MUX module/submodule */ +char* generate_verilog_mux_subckt_name(t_spice_model* spice_model, + int mux_size, char* postfix) { + char* mux_subckt_name = NULL; + + mux_subckt_name = (char*)my_malloc(sizeof(char)*(strlen(spice_model->name) + 5 + + strlen(my_itoa(mux_size)) + strlen(postfix) + 1)); + sprintf(mux_subckt_name, "%s_size%d%s", + spice_model->name, mux_size, postfix); + + return mux_subckt_name; +} + enum e_dump_verilog_port_type convert_spice_model_port_type_to_verilog_port_type(enum e_spice_model_port_type spice_model_port_type) { enum e_dump_verilog_port_type verilog_port_type; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h index a66fd48f2..47b780804 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h @@ -221,6 +221,9 @@ char* generate_verilog_mem_subckt_name(t_spice_model* spice_model, t_spice_model* mem_model, char* postfix); +char* generate_verilog_mux_basis_subckt_name(t_spice_model* spice_model, + int mux_size, char* postfix); + char* generate_verilog_mux_subckt_name(t_spice_model* spice_model, int mux_size, char* postfix); From 32e3a556b9e12ff97318f2e22754adf495777ad3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Jul 2019 09:26:05 -0600 Subject: [PATCH 5/5] bug fixing herited from explicit mapping --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index aa4525e9a..eb736e27e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -3213,7 +3213,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_mux_conf_bits - 1); - fprintf(fp, "is_explicit_mappingf\n"); + fprintf(fp, "`endif\n"); /* Call the MUX SPICE model */