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bug fixed in the example architecture

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tangxifan 2020-04-07 16:03:34 -06:00
parent 628ea3b654
commit 6daee8c2c8
1 changed files with 1 additions and 0 deletions
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openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
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@ -418,6 +418,7 @@
<direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/> <direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
<direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/> <direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
<direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/> <direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
<complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
<mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D"> <mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
<delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/> <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
</mux> </mux>