From 6daee8c2c84673382402063d191fe27ebcdc0cd9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 7 Apr 2020 16:03:34 -0600
Subject: [PATCH] bug fixed in the example architecture

---
 .../k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml  | 1 +
 1 file changed, 1 insertion(+)

diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
index 66d0c9515..bb06c5f39 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
@@ -418,6 +418,7 @@
               <direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
               <direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
               <direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
               <mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
                 <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
               </mux>