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Fix for regression failure. Need to add dfflegalize command in yosys script for dff mapping

This commit is contained in:
Lalit Sharma 2021-03-30 01:26:55 -07:00
parent 7c882dc734
commit 685cd2f297
2 changed files with 6 additions and 0 deletions
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3
openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
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@ -11,6 +11,9 @@ techmap -D NO_LUT -map +/adff2dff.v
synth -top ${TOP_MODULE} -flatten
clean
# Map flip-flops
dfflegalize -cell $_DFF_P_ 0 -cell $_DFF_P??_ 0 -cell $_DFF_N_ 0 -cell $_DFF_N??_ 0
# LUT mapping
abc -lut ${LUT_SIZE}

3
openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys
View File

@ -11,6 +11,9 @@ techmap -D NO_LUT -map +/adff2dff.v
synth -top ${TOP_MODULE} -flatten
clean
# Map flip-flops
dfflegalize -cell $_DFF_P_ 0 -cell $_DFF_P??_ 0 -cell $_DFF_N_ 0 -cell $_DFF_N??_ 0
# LUT mapping
abc -lut ${LUT_SIZE}