From 685cd2f2974d31df1ee26386e46424435458bf11 Mon Sep 17 00:00:00 2001 From: Lalit Sharma Date: Tue, 30 Mar 2021 01:26:55 -0700 Subject: [PATCH] Fix for regression failure. Need to add dfflegalize command in yosys script for dff mapping --- openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys | 3 +++ openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys | 3 +++ 2 files changed, 6 insertions(+) diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys index aeaded4b5..80e0e7d77 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys @@ -11,6 +11,9 @@ techmap -D NO_LUT -map +/adff2dff.v synth -top ${TOP_MODULE} -flatten clean +# Map flip-flops +dfflegalize -cell $_DFF_P_ 0 -cell $_DFF_P??_ 0 -cell $_DFF_N_ 0 -cell $_DFF_N??_ 0 + # LUT mapping abc -lut ${LUT_SIZE} diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys index edcce4c23..6b4b55811 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys @@ -11,6 +11,9 @@ techmap -D NO_LUT -map +/adff2dff.v synth -top ${TOP_MODULE} -flatten clean +# Map flip-flops +dfflegalize -cell $_DFF_P_ 0 -cell $_DFF_P??_ 0 -cell $_DFF_N_ 0 -cell $_DFF_N??_ 0 + # LUT mapping abc -lut ${LUT_SIZE}