diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
index aeaded4b5..80e0e7d77 100644
--- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
+++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
@@ -11,6 +11,9 @@ techmap -D NO_LUT -map +/adff2dff.v
 synth -top ${TOP_MODULE} -flatten
 clean
 
+# Map flip-flops
+dfflegalize -cell $_DFF_P_ 0 -cell $_DFF_P??_ 0 -cell $_DFF_N_ 0 -cell $_DFF_N??_ 0
+
 # LUT mapping
 abc -lut ${LUT_SIZE}
 
diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys
index edcce4c23..6b4b55811 100644
--- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys
+++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys
@@ -11,6 +11,9 @@ techmap -D NO_LUT -map +/adff2dff.v
 synth -top ${TOP_MODULE} -flatten
 clean
 
+# Map flip-flops
+dfflegalize -cell $_DFF_P_ 0 -cell $_DFF_P??_ 0 -cell $_DFF_N_ 0 -cell $_DFF_N??_ 0
+
 # LUT mapping
 abc -lut ${LUT_SIZE}