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Code Issues Projects Releases Wiki Activity

renaming design flows in documentation

This commit is contained in:
tangxifan 2020-05-24 23:03:54 -06:00
parent 011ce5cdf6
commit 35536ee594
2 changed files with 2 additions and 2 deletions
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2
docs/source/tutorials/design_flow/index.rst
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@ -7,4 +7,4 @@ Design Flows
.. toctree:: .. toctree::
:maxdepth: 2 :maxdepth: 2
sc_flow verilog_to_gds2

2
docs/source/tutorials/design_flow/sc_flow.rst → docs/source/tutorials/design_flow/verilog_to_gds2.rst
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@ -1,4 +1,4 @@
From Verilog to Layout From Verilog to GDSII
~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~
The generated Verilog code can be used through a semi-custom design flow to generate the layout. The generated Verilog code can be used through a semi-custom design flow to generate the layout.