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Merge branch 'master' into gg_ci_cd_dev

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tangxifan 2021-12-01 23:12:18 -08:00 committed by GitHub
parent 7d248c399d 9f1d47b6c0
commit 1ec99b98c5
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2 changed files with 8 additions and 10 deletions
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8
.github/workflows/build.yml vendored
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@ -170,12 +170,8 @@ jobs:
openfpga/openfpga openfpga/openfpga
vpr/libvpr.a vpr/libvpr.a
vpr/vpr vpr/vpr
yosys/install/share/ yosys/install/share
yosys/install/bin/yosys yosys/install/bin
yosys/install/bin/yosys-abc
yosys/install/bin/yosys-config
yosys/install/bin/yosys-filterlib
yosys/install/bin/yosys-smtbmc
openfpga_flow openfpga_flow
openfpga.sh openfpga.sh
docker_distribution: docker_distribution:

10
docs/source/contact.rst
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@ -13,9 +13,11 @@ Technical Details about FPGA-SPICE/Verilog/Bitstream/SDC:
Dr. Xifan Tang Dr. Xifan Tang
xifan.tang@utah.edu xifan@osfpga.org
.. Technical Details about layout auto-generation Technical Details about physical design
.. Edouard Giacomin
.. edouard.giacomin@utah.edu Ganesh Gore
ganesh.gore@utah.edu