diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 38aa97d66..445e52ee8 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -170,12 +170,8 @@ jobs:
             openfpga/openfpga
             vpr/libvpr.a
             vpr/vpr
-            yosys/install/share/
-            yosys/install/bin/yosys
-            yosys/install/bin/yosys-abc
-            yosys/install/bin/yosys-config
-            yosys/install/bin/yosys-filterlib
-            yosys/install/bin/yosys-smtbmc
+            yosys/install/share
+            yosys/install/bin
             openfpga_flow
             openfpga.sh
   docker_distribution:
diff --git a/docs/source/contact.rst b/docs/source/contact.rst
index 1e7e1e801..ae44e73f1 100644
--- a/docs/source/contact.rst
+++ b/docs/source/contact.rst
@@ -13,9 +13,11 @@ Technical Details about FPGA-SPICE/Verilog/Bitstream/SDC:
 
 Dr. Xifan Tang
 
-xifan.tang@utah.edu
+xifan@osfpga.org
 
-.. Technical Details about layout auto-generation
-.. Edouard Giacomin
-.. edouard.giacomin@utah.edu
+Technical Details about physical design
+
+Ganesh Gore
+
+ganesh.gore@utah.edu