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minor tuning on the delay assignment

This commit is contained in:
tangxifan 2019-08-21 23:11:54 -06:00
parent 7b0c55ce15
commit 1be5632e92
1 changed files with 1 additions and 1 deletions
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2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp
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@ -71,7 +71,7 @@ void print_verilog_submodule_timing(std::fstream& fp,
fp << generate_verilog_port(VERILOG_PORT_CONKT, sink_port_info) << ")";
fp << " = ";
fp << "(" << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, SPICE_MODEL_DELAY_RISE) / verilog_sim_timescale;
fp << " , ";
fp << ", ";
fp << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, SPICE_MODEL_DELAY_FALL) / verilog_sim_timescale << ")";
fp << ";" << std::endl;
}