diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp
index 191e1f7d3..3ddf25c03 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp
@@ -71,7 +71,7 @@ void print_verilog_submodule_timing(std::fstream& fp,
      fp << generate_verilog_port(VERILOG_PORT_CONKT, sink_port_info) << ")";
      fp << " = ";
      fp << "(" << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, SPICE_MODEL_DELAY_RISE) / verilog_sim_timescale;
-     fp << " , ";
+     fp << ", ";
      fp << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, SPICE_MODEL_DELAY_FALL) / verilog_sim_timescale << ")";
      fp << ";" << std::endl;
   }