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[Test] Rework comments on runtime

This commit is contained in:
tangxifan 2021-02-22 15:25:57 -07:00
parent 4803b0ce42
commit 19f6b221b1
2 changed files with 3 additions and 9 deletions
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8
openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf
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@ -12,13 +12,7 @@ power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = false power_analysis = false
spice_output=false spice_output=false
verilog_output=true verilog_output=true
timeout_each_job = 2*60 timeout_each_job = 1*60
# Due to the limitation in ACE2 which cannot output .blif files
# with correct multi-clock assignments to .latch lines
# We have to use the vpr_blif flow where the .blif is modified
# based on yosys outputs with correct clock assignment!
# TODO: This limitation should be removed and we should use yosys_vpr flow!!!
#fpga_flow=vpr_blif
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
[OpenFPGA_SHELL] [OpenFPGA_SHELL]

4
openfpga_flow/tasks/quicklogic_tests/sdc_controller_test/config/task.conf
View File

@ -12,10 +12,10 @@ power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = false power_analysis = false
spice_output=false spice_output=false
verilog_output=true verilog_output=true
# Runtime is around 15 minutes # Runtime is around 3 minutes
# But it can be efficiently reduced by improving synthesis script # But it can be efficiently reduced by improving synthesis script
# (See detailed comments in Synthesis parameter section) # (See detailed comments in Synthesis parameter section)
timeout_each_job = 15*60 timeout_each_job = 5*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
[OpenFPGA_SHELL] [OpenFPGA_SHELL]