diff --git a/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf
index 48b137111..6918c7069 100644
--- a/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf
+++ b/openfpga_flow/tasks/quicklogic_tests/counter_5clock_test/config/task.conf
@@ -12,13 +12,7 @@ power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
 power_analysis = false
 spice_output=false
 verilog_output=true
-timeout_each_job = 2*60
-# Due to the limitation in ACE2 which cannot output .blif files 
-# with correct multi-clock assignments to .latch lines
-# We have to use the vpr_blif flow where the .blif is modified
-# based on yosys outputs with correct clock assignment!
-# TODO: This limitation should be removed and we should use yosys_vpr flow!!!
-#fpga_flow=vpr_blif
+timeout_each_job = 1*60
 fpga_flow=yosys_vpr
 
 [OpenFPGA_SHELL]
diff --git a/openfpga_flow/tasks/quicklogic_tests/sdc_controller_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/sdc_controller_test/config/task.conf
index dcca98def..01321050b 100644
--- a/openfpga_flow/tasks/quicklogic_tests/sdc_controller_test/config/task.conf
+++ b/openfpga_flow/tasks/quicklogic_tests/sdc_controller_test/config/task.conf
@@ -12,10 +12,10 @@ power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
 power_analysis = false
 spice_output=false
 verilog_output=true
-# Runtime is around 15 minutes 
+# Runtime is around 3 minutes 
 # But it can be efficiently reduced by improving synthesis script
 # (See detailed comments in Synthesis parameter section)
-timeout_each_job = 15*60
+timeout_each_job = 5*60
 fpga_flow=yosys_vpr
 
 [OpenFPGA_SHELL]