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Merge pull request #244 from lnis-uofu/synth_verilog_test_deployment 

Deploy synthesizable verilog test to CI
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ganeshgore 2021-02-18 10:46:19 -07:00 committed by GitHub
parent 1a23f76bd0 9004e28d47
commit 122218dfd3
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openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh
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@ -95,6 +95,9 @@ run-task fpga_verilog/mux_design/no_const_input --debug --show_thread_logs
echo -e "Testing Verilog generation with behavioral description"; echo -e "Testing Verilog generation with behavioral description";
run-task fpga_verilog/behavioral_verilog --debug --show_thread_logs run-task fpga_verilog/behavioral_verilog --debug --show_thread_logs
echo -e "Testing synthesizable Verilog generation with external standard cells";
run-task fpga_verilog/synthesizable_verilog --debug --show_thread_logs
echo -e "Testing implicit Verilog generation"; echo -e "Testing implicit Verilog generation";
run-task fpga_verilog/implicit_verilog --debug --show_thread_logs run-task fpga_verilog/implicit_verilog --debug --show_thread_logs