From 47cb1cc2d40e54b0bd241be68f59904dedd7f57d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 17 Feb 2021 16:13:15 -0700 Subject: [PATCH] [Test] Deploy synthesizable verilog test to CI --- openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh index 2f5b917dc..3d7db9b0c 100755 --- a/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/fpga_verilog_reg_test.sh @@ -95,6 +95,9 @@ run-task fpga_verilog/mux_design/no_const_input --debug --show_thread_logs echo -e "Testing Verilog generation with behavioral description"; run-task fpga_verilog/behavioral_verilog --debug --show_thread_logs +echo -e "Testing synthesizable Verilog generation with external standard cells"; +run-task fpga_verilog/synthesizable_verilog --debug --show_thread_logs + echo -e "Testing implicit Verilog generation"; run-task fpga_verilog/implicit_verilog --debug --show_thread_logs