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[HDL] Update the WL CCFF HDL modeling by adding Write-Enable signals

This commit is contained in:
tangxifan 2021-10-01 17:06:35 -07:00
parent 7ba5d27ea7
commit 0b06820177
1 changed files with 4 additions and 2 deletions
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6
openfpga_flow/openfpga_cell_library/verilog/dff.v
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@ -475,6 +475,7 @@ module WL_DFFRQ (
input RST, // Reset input input RST, // Reset input
input CK, // Clock Input input CK, // Clock Input
input SIN, // Data Input input SIN, // Data Input
input WEN, // Write-enable
output SOUT, // Q output output SOUT, // Q output
output WLW // Drive WL write signals output WLW // Drive WL write signals
); );
@ -490,7 +491,7 @@ end else begin
end end
assign SOUT = q_reg; assign SOUT = q_reg;
assign WLW = q_reg; assign WLW = WEN ? q_reg : 1'b0;
endmodule //End Of Module endmodule //End Of Module
@ -503,6 +504,7 @@ module WLR_DFFRQ (
input RST, // Reset input input RST, // Reset input
input CK, // Clock Input input CK, // Clock Input
input SIN, // Data Input input SIN, // Data Input
input WEN, // Write-enable
output SOUT, // Q output output SOUT, // Q output
output WLW, // Drive WL write signals output WLW, // Drive WL write signals
output WLR // Drive WL read signals output WLR // Drive WL read signals
@ -519,7 +521,7 @@ end else begin
end end
assign SOUT = q_reg; assign SOUT = q_reg;
assign WLW = q_reg; assign WLW = WEN ? q_reg : 1'b0;
assign WLR = 1'b0; // Use a constant output just for simple testing assign WLR = 1'b0; // Use a constant output just for simple testing
endmodule //End Of Module endmodule //End Of Module