From 0b068201774ccec39ba1608fb1bee3995a2fc23a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 1 Oct 2021 17:06:35 -0700
Subject: [PATCH] [HDL] Update the WL CCFF HDL modeling by adding Write-Enable
 signals

---
 openfpga_flow/openfpga_cell_library/verilog/dff.v | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/openfpga_cell_library/verilog/dff.v b/openfpga_flow/openfpga_cell_library/verilog/dff.v
index da641d785..b03b2ba2d 100644
--- a/openfpga_flow/openfpga_cell_library/verilog/dff.v
+++ b/openfpga_flow/openfpga_cell_library/verilog/dff.v
@@ -475,6 +475,7 @@ module WL_DFFRQ (
   input RST, // Reset input
   input CK, // Clock Input
   input SIN, // Data Input
+  input WEN, // Write-enable
   output SOUT, // Q output
   output WLW // Drive WL write signals
 );
@@ -490,7 +491,7 @@ end else begin
 end
 
 assign SOUT = q_reg;
-assign WLW = q_reg;
+assign WLW = WEN ? q_reg : 1'b0;
 
 endmodule //End Of Module
 
@@ -503,6 +504,7 @@ module WLR_DFFRQ (
   input RST, // Reset input
   input CK, // Clock Input
   input SIN, // Data Input
+  input WEN, // Write-enable
   output SOUT, // Q output
   output WLW, // Drive WL write signals
   output WLR // Drive WL read signals
@@ -519,7 +521,7 @@ end else begin
 end
 
 assign SOUT = q_reg;
-assign WLW = q_reg;
+assign WLW = WEN ? q_reg : 1'b0;
 assign WLR = 1'b0; // Use a constant output just for simple testing
 
 endmodule //End Of Module