Read the XML file about programmable clock network (see details in :ref:`file_formats_clock_network`)
..option:: --file <string> or -f <string>
Specify the file name. For example, ``--file clock_network.xml``
..option:: --verbose
Show verbose log
write_openfpga_clock_arch
~~~~~~~~~~~~~~~~~~~~~~~~~
Write the OpenFPGA programmable clock network to an XML file
..option:: --file <string> or -f <string>
Specify the file name. For example, ``--file clock_network_echo.xml``.
See details about file format at :ref:`file_formats_clock_network`.
..option:: --verbose
Show verbose log
append_clock_rr_graph
~~~~~~~~~~~~~~~~~~~~~
Build the routing resource graph based on an defined programmable clock network, and append it to the existing routing resource graph built by VPR.
Use command :ref:`openfpga_setup_command_read_openfpga_clock_arch`` to load the clock network.
..option:: --verbose
Show verbose log
route_clock_rr_graph
~~~~~~~~~~~~~~~~~~~~
Route clock signals on the built routing resource graph which contains a programmable clock network.
Clock signals will be auto-detected and routed based on pin constraints which are provided by users.
..option:: --pin_constraints_file <string> or -pcf <string>
Specify the *Pin Constraints File* (PCF) when the clock network contains multiple clock pins. For example, ``-pin_constraints_file pin_constraints.xml``
Strongly recommend for multi-clock network. See detailed file format about :ref:`file_format_pin_constraints_file`.
Write the internal structure of General Switch Blocks (GSBs) across a FPGA fabric, including the interconnection between the nodes and node-level details, to XML files
Exclude routing resource graph information from output files, e.g., node id as well as other attributes. This is useful to check the connection inside GSBs purely.
..option:: --exclude <string>
Exclude part of the GSB data to be outputted. Can be [``sb``|``cbx``|``cby``]. Users can exclude multiple parts by using a splitter ``,``.
..note:: Suggest to skip the similar fix-up applied by VPR through options ``--skip_sync_clustering_and_routing_results on`` when calling vpr in openfpga shell.
..warning:: This feature has been integrated into VPR to provide accurate timing analysis results at post-routing stage. However, this command provides a light fix-up (not as thorough as the one in VPR) but bring more flexibility in support some architecture without local routing. Suggest to enable it when your architecture does not have local routing for *Look-Up Tables* (LUTs) but you want to enable logic equivalent for input pins of LUTs
..warning:: This command may be deprecated in future
Enable compression on routing architecture modules. Strongly recommend this as it will minimize the number of routing modules to be outputted. It can reduce the netlist size significantly.
Create only frame views of the module graph. When enabled, top-level module will not include any nets. This option is made for save runtime and memory.
Output current fabric key to an XML file. For example, ``write_fabric_key --file fpga_2x2.xml`` See details in :ref:`file_formats_fabric_key`.
..note:: This command can output module-level keys while the ``--write_fabric_key`` option in command ``build_fabric`` does NOT support! Strongly recommend to use this command to obtain fabric key.
..option:: --file <string> or -f <string>
Specify the file name. For example, ``--file fabric_key_echo.xml``.
Add a wrapper module ``fpga_core`` as an intermediate layer to FPGA fabric. After this command, the existing module ``fpga_top`` will remain the top-level module while there is a new module ``fpga_core`` under it. Under fpga_core, there will be the detailed building blocks.
This is optional. Specify the I/O naming rules when connecting I/Os of ``fpga_core`` module to the top-level module ``fpga_top``. If not defined, the ``fpga_top`` will be the same as ``fpga_core`` w.r.t. ports. See details about the file format of I/O naming rules in :ref:`file_formats_io_naming_file`.
This is optional. Specify the instance name to be used when instanciate the ``fpga_core`` module under the top-level module ``fpga_top``. If not defined, by default it is ``fpga_core_inst``.
..option:: --frame_view
Create only frame views of the module graph. When enabled, top-level module will not include any nets. This option is made for save runtime and memory.
..warning:: Recommend to turn the option on when bitstream generation is the only purpose of the flow. Do not use it when you need generate netlists!
Specify at which depth of the fabric module graph should the writer stop outputting. The root module start from depth 0. For example, if you want a two-level hierarchy, you should specify depth as 1.
Convert a Pin Constraint File (.pcf, see details in :ref:`file_format_pcf_file`) to a `placement file <https://docs.verilogtorouting.org/en/latest/vpr/file_formats/#placement-file-format-place>`_)
Specify the path to the pin table file, which describes the pin mapping between chip I/Os and FPGA I/Os. See details in :ref:`file_format_pin_table_file`
Specify the naming convention for ports in pin table files from which pin direction can be inferred. Can be [``explicit``|``quicklogic``]. When ``explicit`` is selected, pin direction is inferred based on the explicit definition in a column of pin table file, e.g., GPIO direction (see details in :ref:`file_format_pin_table_file`). When ``quicklogic`` is selected, pin direction is inferred by port name: a port whose postfix is ``_A2F`` is an input, while a port whose postfix is ``_A2F`` is an output. By default, it is ``explicit``.
