128 lines
4.0 KiB
ReStructuredText
128 lines
4.0 KiB
ReStructuredText
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.. _openfpga_setup_commands:
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Setup OpenFPGA
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--------------
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read_openfpga_arch
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~~~~~~~~~~~~~~~~~~
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Read the XML file about architecture description (see details in :ref:`arch_generality`)
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- ``--file`` or ``-f`` Specify the file name
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- ``--verbose`` Show verbose log
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write_openfpga_arch
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~~~~~~~~~~~~~~~~~~~
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Write the OpenFPGA XML architecture file to a file
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- ``--file`` or ``-f`` Specify the file name
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- ``--verbose`` Show verbose log
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read_openfpga_simulation_setting
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Read the XML file about simulation settings (see details in :ref:`simulation_setting`)
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- ``--file`` or ``-f`` Specify the file name
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- ``--verbose`` Show verbose log
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write_openfpga_simulation_setting
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Write the OpenFPGA XML simulation settings to a file
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- ``--file`` or ``-f`` Specify the file name
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- ``--verbose`` Show verbose log
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link_openfpga_arch
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~~~~~~~~~~~~~~~~~~
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Annotate the OpenFPGA architecture to VPR data base
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- ``--activity_file`` Specify the signal activity file
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- ``--sort_gsb_chan_node_in_edges`` Sort the edges for the routing tracks in General Switch Blocks (GSBs). Strongly recommand to turn this on for uniquifying the routing modules
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- ``--verbose`` Show verbose log
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write_gsb_to_xml
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~~~~~~~~~~~~~~~~
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Write the internal structure of General Switch Blocks (GSBs) across a FPGA fabric, including the interconnection between the nodes and node-level details, to XML files
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- ``--file`` or ``-f`` Specify the output directory of the XML files. Each GSB will be written to an indepedent XML file
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- ``--verbose`` Show verbose log
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.. note:: This command is used to help users to study the difference between GSBs
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check_netlist_naming_conflict
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Check and correct any naming conflicts in the BLIF netlist
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This is strongly recommended. Otherwise, the outputted Verilog netlists may not be compiled successfully.
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.. warning:: This command may be deprecated in future when it is merged to VPR upstream
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- ``--fix`` Apply fix-up to the names that violate the syntax
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- ``--report <.xml>`` Report the naming fix-up to a log file
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pb_pin_fixup
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~~~~~~~~~~~~
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Apply fix-up to clustering nets based on routing results
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This is strongly recommended. Otherwise, the bitstream generation may be wrong
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.. warning:: This command may be deprecated in future when it is merged to VPR upstream
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- ``--verbose`` Show verbose log
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lut_truth_table_fixup
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~~~~~~~~~~~~~~~~~~~~~
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Apply fix-up to Look-Up Table truth tables based on packing results
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.. warning:: This command may be deprecated in future when it is merged to VPR upstream
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- ``--verbose`` Show verbose log
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.. _cmd_build_fabric:
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build_fabric
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~~~~~~~~~~~~
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Build the module graph.
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- ``--compress_routing`` Enable compression on routing architecture modules. Strongly recommend this as it will minimize the number of routing modules to be outputted. It can reduce the netlist size significantly.
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- ``--duplicate_grid_pin`` Enable pin duplication on grid modules. This is optional unless ultra-dense layout generation is needed
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- ``--load_fabric_key <xml_file>`` Load an external fabric key from an XML file.
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- ``--generate_fabric_key`` Generate a fabric key in a random way
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- ``--write_fabric_key <xml_file>`` Output current fabric key to an XML file
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- ``--verbose`` Show verbose log
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.. note:: This is a must-run command before launching FPGA-Verilog, FPGA-Bitstream, FPGA-SDC and FPGA-SPICE
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write_fabric_hierarchy
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~~~~~~~~~~~~~~~~~~~~~~
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Write the hierarchy of FPGA fabric graph to a plain-text file
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- ``--file`` or ``-f`` Specify the file name to write the hierarchy.
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- ``--depth`` Specify at which depth of the fabric module graph should the writer stop outputting. The root module start from depth 0. For example, if you want a two-level hierarchy, you should specify depth as 1.
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- ``--verbose`` Show verbose log
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.. note:: This file is designed for hierarchical PnR flow, which requires the tree of Multiple-Instanced-Blocks (MIBs).
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