91 lines
1.3 KiB
Coq
91 lines
1.3 KiB
Coq
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////////////////////////////////////////
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// //
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// Synchronized adder benchmark //
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// //
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////////////////////////////////////////
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module sync_4bits_add(
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clk,
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rst,
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a0,
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a1,
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a2,
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a3,
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b0,
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b1,
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b2,
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b3,
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cin,
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sumout0,
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sumout1,
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sumout2,
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sumout3,
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cout);
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input clk;
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input rst;
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input a0;
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input a1;
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input a2;
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input a3;
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input b0;
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input b1;
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input b2;
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input b3;
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input cin;
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output sumout0;
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output sumout1;
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output sumout2;
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output sumout3;
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output reg cout;
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wire[3:0] a;
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wire[3:0] b;
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reg[3:0] sumout;
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reg[3:0] reg_a;
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reg[3:0] reg_b;
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reg reg_cin;
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wire[4:0] int_sum;
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assign a[3] = a3;
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assign a[2] = a2;
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assign a[1] = a1;
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assign a[0] = a0;
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assign b[3] = b3;
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assign b[2] = b2;
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assign b[1] = b1;
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assign b[0] = b0;
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assign sumout3 = sumout[3];
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assign sumout2 = sumout[2];
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assign sumout1 = sumout[1];
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assign sumout0 = sumout[0];
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assign int_sum = reg_a + reg_b + reg_cin;
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always@(posedge clk or posedge rst) begin
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if(rst) begin
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reg_a <= 4'h0;
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reg_b <= 4'h0;
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reg_cin <= 1'h0;
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end
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else begin
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reg_a <= a;
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reg_b <= b;
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reg_cin <= cin;
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end
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end
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always@(posedge clk or posedge rst) begin
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if(rst) begin
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sumout <= 4'h0;
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cout <= 1'h0;
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end
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else begin
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sumout <= int_sum[3:0];
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cout <= int_sum[4];
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end
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end
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endmodule
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