2019-04-26 13:23:47 -05:00
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#! /bin/csh -f
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# Example of how to run vpr
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# Set variables
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# For FPGA-Verilog ONLY
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2019-05-10 15:07:32 -05:00
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set benchmark = s298_prevpr
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set verilog_output_dirname = ${benchmark}_Verilog
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set verilog_output_dirpath = $PWD
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2019-04-26 13:23:47 -05:00
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set modelsim_ini_file = /uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/modelsim.ini
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# VPR critical inputs
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#set arch_xml_file = ARCH/k6_N10_MD_tsmc40nm_chain_TT.xml
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#set arch_xml_file = ARCH/k8_N10_SC_tsmc40nm_chain_TT_stratixIV_lookalike.xml
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2019-05-10 15:07:32 -05:00
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set arch_xml_file = ARCH/k6_N10_sram_chain_HC_template.xml
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2019-04-26 13:23:47 -05:00
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#set arch_xml_file = ARCH/ed_stdcell.xml
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#set arch_xml_file = ARCH/k6_N10_sram_chain_FC_tsmc40.xml
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#set arch_xml_file = ARCH/k6_N10_SC_tsmc40nm_chain_TT.xml
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#set arch_xml_file = ARCH/k6_N10_SC_tsmc40nm_chain_TT_yosys.xml
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#set arch_xml_file = ARCH/k6_N10_sram_chain_SC_gf130_2x2.xml
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#set verilog_reference = ${PWD}/Circuits/alu4_K6_N10_ace.v
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#set blif_file = Circuits/shiftReg.blif
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#set act_file = Circuits/shiftReg.act
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2019-05-10 15:07:32 -05:00
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set blif_file = Circuits/$benchmark.blif
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set act_file = Circuits/$benchmark.act
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set verilog_reference = ${PWD}/Circuits/$benchmark.v
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2019-04-26 13:23:47 -05:00
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#set blif_file = Circuits/frisc.blif
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#set act_file = Circuits/frisc.act
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#set blif_file = Circuits/elliptic.blif
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#set act_file = Circuits/elliptic.act
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set vpr_route_chan_width = 200
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# Step A: Make sure a clean start
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# Recompile if needed
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#make clean
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#make -j32
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# Remove previous designs
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rm -rf $verilog_output_dirpath/$verilog_output_dirname
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2019-05-28 15:15:24 -05:00
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rm -rf $verilog_output_dirpath/$verilog_output_dirname\_compact
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2019-04-26 13:23:47 -05:00
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# Run VPR
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#valgrind
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2019-05-24 17:14:46 -05:00
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./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_verilog_print_report_timing_tcl
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2019-04-26 13:23:47 -05:00
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2019-05-26 00:41:46 -05:00
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./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname\_compact --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_modelsim_autodeck $modelsim_ini_file --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_x2p_compact_routing_hierarchy --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_verilog_print_report_timing_tcl
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2019-04-26 13:23:47 -05:00
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