2019-08-12 17:45:33 -05:00
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/**********************************************************
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* MIT License
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*
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* Copyright (c) 2018 LNIS - The University of Utah
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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***********************************************************************/
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/************************************************************************
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* Filename: check_circuit_library.cpp
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* Created by: Xifan Tang
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* Change history:
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* +-------------------------------------+
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* | Date | Author | Notes
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* +-------------------------------------+
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* | 2019/08/12 | Xifan Tang | Created
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* +-------------------------------------+
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***********************************************************************/
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2019-08-13 14:25:23 -05:00
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/************************************************************************
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* Function to perform fundamental checking for the circuit library
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* such as
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* 1. if default circuit models are defined
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* 2. if any circuit models shared the same name or prefix
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* 3. if nay circuit model miss mandatory ports
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***********************************************************************/
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2019-08-12 17:45:33 -05:00
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/* Header files should be included in a sequence */
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/* Standard header files required go first */
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2019-08-13 14:25:23 -05:00
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#include "vtr_assert.h"
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2019-08-12 17:45:33 -05:00
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#include "util.h"
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2019-08-13 14:25:23 -05:00
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2019-08-12 17:45:33 -05:00
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#include "check_circuit_library.h"
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2019-08-13 14:25:23 -05:00
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/************************************************************************
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* Circuit models have unique names, return the number of errors
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* If not found, we give an error
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***********************************************************************/
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2019-08-12 17:45:33 -05:00
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static
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size_t check_circuit_library_unique_names(const CircuitLibrary& circuit_lib) {
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size_t num_err = 0;
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2019-08-19 21:43:35 -05:00
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for (size_t i = 0; i < circuit_lib.num_models(); ++i) {
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2019-08-12 17:45:33 -05:00
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/* Skip for the last element, because the inner loop will access it */
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2019-08-19 21:43:35 -05:00
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if (i == circuit_lib.num_models() - 1) {
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2019-08-12 17:45:33 -05:00
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continue;
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}
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/* Get the name of reference */
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2019-08-19 21:43:35 -05:00
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const std::string& i_name = circuit_lib.model_name(CircuitModelId(i));
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for (size_t j = i + 1; j < circuit_lib.num_models(); ++j) {
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2019-08-12 17:45:33 -05:00
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/* Compare the name of candidate */
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2019-08-19 21:43:35 -05:00
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const std::string& j_name = circuit_lib.model_name(CircuitModelId(j));
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2019-08-12 17:45:33 -05:00
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/* Compare the name and skip for different names */
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if (0 != i_name.compare(j_name)) {
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continue;
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}
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vpr_printf(TIO_MESSAGE_ERROR,
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"Circuit model(index=%d) and (index=%d) share the same name, which is invalid!\n",
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i , j, i_name.c_str());
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/* Incremental the counter for errors */
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num_err++;
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}
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}
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return num_err;
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}
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2019-08-13 14:25:23 -05:00
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/************************************************************************
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* Circuit models have unique names, return the number of errors
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* If not found, we give an error
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***********************************************************************/
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2019-08-12 17:45:33 -05:00
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static
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size_t check_circuit_library_unique_prefix(const CircuitLibrary& circuit_lib) {
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size_t num_err = 0;
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2019-08-19 21:43:35 -05:00
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for (size_t i = 0; i < circuit_lib.num_models(); ++i) {
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2019-08-12 17:45:33 -05:00
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/* Skip for the last element, because the inner loop will access it */
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2019-08-19 21:43:35 -05:00
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if (i == circuit_lib.num_models() - 1) {
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2019-08-12 17:45:33 -05:00
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continue;
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}
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/* Get the name of reference */
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2019-08-19 21:43:35 -05:00
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const std::string& i_prefix = circuit_lib.model_prefix(CircuitModelId(i));
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for (size_t j = i + 1; j < circuit_lib.num_models(); ++j) {
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2019-08-12 17:45:33 -05:00
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/* Compare the name of candidate */
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2019-08-19 21:43:35 -05:00
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const std::string& j_prefix = circuit_lib.model_prefix(CircuitModelId(j));
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2019-08-12 17:45:33 -05:00
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/* Compare the name and skip for different prefix */
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if (0 != i_prefix.compare(j_prefix)) {
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continue;
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}
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vpr_printf(TIO_MESSAGE_ERROR,
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"Circuit model(name=%s) and (name=%s) share the same prefix, which is invalid!\n",
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2019-08-19 21:43:35 -05:00
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circuit_lib.model_name(CircuitModelId(i)).c_str(),
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circuit_lib.model_name(CircuitModelId(j)).c_str(),
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2019-08-12 17:45:33 -05:00
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i_prefix.c_str());
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/* Incremental the counter for errors */
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num_err++;
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}
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}
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return num_err;
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}
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2019-08-13 14:25:23 -05:00
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/************************************************************************
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* A generic function to check the port list of a circuit model in a given type
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* If not found, we give an error
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***********************************************************************/
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2019-08-12 17:45:33 -05:00
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static
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size_t check_circuit_model_required(const CircuitLibrary& circuit_lib,
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const enum e_spice_model_type& circuit_model_type_to_check) {
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size_t num_err = 0;
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/* We must have an IOPAD*/
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2019-08-19 21:43:35 -05:00
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if ( 0 == circuit_lib.models_by_type(circuit_model_type_to_check).size()) {
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2019-08-12 17:45:33 -05:00
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vpr_printf(TIO_MESSAGE_ERROR,
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"At least one %s circuit model is required!\n",
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CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_model_type_to_check)]);
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/* Incremental the counter for errors */
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num_err++;
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}
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return num_err;
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}
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2019-08-13 14:25:23 -05:00
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/************************************************************************
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* A generic function to check the port list of a circuit model in a given type
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* If not found, we give an error
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***********************************************************************/
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size_t check_one_circuit_model_port_required(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model,
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const std::vector<enum e_spice_model_port_type>& port_types_to_check) {
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size_t num_err = 0;
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for (const auto& port_type: port_types_to_check) {
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2019-08-20 16:14:28 -05:00
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if (0 == circuit_lib.model_ports_by_type(circuit_model, port_type).size()) {
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2019-08-13 14:25:23 -05:00
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vpr_printf(TIO_MESSAGE_ERROR,
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"%s circuit model(name=%s) does not have %s port\n",
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2019-08-19 21:43:35 -05:00
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CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.model_type(circuit_model))],
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circuit_lib.model_name(circuit_model).c_str(),
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2019-08-13 14:25:23 -05:00
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CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type)]);
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/* Incremental the counter for errors */
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num_err++;
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}
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}
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return num_err;
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}
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/************************************************************************
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* A generic function to check the port size of a given circuit model
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* if the port size does not match, we give an error
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***********************************************************************/
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size_t check_one_circuit_model_port_size_required(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model,
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const CircuitPortId& circuit_port,
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const size_t& port_size_to_check) {
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size_t num_err = 0;
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2019-08-20 16:14:28 -05:00
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if (port_size_to_check != circuit_lib.port_size(circuit_port)) {
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2019-08-13 14:25:23 -05:00
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vpr_printf(TIO_MESSAGE_ERROR,
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"Port of circuit model(name=%s) does not have a port(type=%s) of size=%d.\n",
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2019-08-19 21:43:35 -05:00
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circuit_lib.model_name(circuit_model).c_str(),
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2019-08-20 16:14:28 -05:00
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CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(circuit_port))],
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2019-08-13 14:25:23 -05:00
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port_size_to_check);
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/* Incremental the counter for errors */
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num_err++;
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}
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return num_err;
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}
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/************************************************************************
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* A generic function to check the port size of a given circuit model
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* if the number of ports in the given type does not match, we give an error
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* for each port, if the port size does not match, we give an error
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***********************************************************************/
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size_t check_one_circuit_model_port_type_and_size_required(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model,
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const enum e_spice_model_port_type& port_type_to_check,
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const size_t& num_ports_to_check,
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const size_t& port_size_to_check,
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const bool& include_global_ports) {
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size_t num_err = 0;
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2019-08-20 19:13:24 -05:00
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std::vector<CircuitPortId> ports = circuit_lib.model_ports_by_type(circuit_model, port_type_to_check, false == include_global_ports);
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2019-08-13 14:25:23 -05:00
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if (num_ports_to_check != ports.size()) {
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vpr_printf(TIO_MESSAGE_ERROR,
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"Expect %d %s ports for a %s circuit model, but only have %d %s ports!\n",
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num_ports_to_check,
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CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type_to_check)],
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2019-08-19 21:43:35 -05:00
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CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_lib.model_type(circuit_model))],
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2019-08-13 14:25:23 -05:00
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CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(port_type_to_check)],
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ports.size());
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num_err++;
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}
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for (const auto& port : ports) {
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num_err += check_one_circuit_model_port_size_required(circuit_lib,
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circuit_model,
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port, port_size_to_check);
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}
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return num_err;
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}
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/************************************************************************
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* A generic function to check the port list of circuit models in a given type
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* If not found, we give an error
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***********************************************************************/
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2019-08-12 17:45:33 -05:00
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static
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size_t check_circuit_model_port_required(const CircuitLibrary& circuit_lib,
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const enum e_spice_model_type& circuit_model_type_to_check,
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const std::vector<enum e_spice_model_port_type>& port_types_to_check) {
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size_t num_err = 0;
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2019-08-19 21:43:35 -05:00
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for (const auto& id : circuit_lib.models_by_type(circuit_model_type_to_check)) {
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2019-08-13 14:25:23 -05:00
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num_err += check_one_circuit_model_port_required(circuit_lib, id, port_types_to_check);
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2019-08-12 17:45:33 -05:00
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}
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return num_err;
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}
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2019-08-13 14:25:23 -05:00
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/************************************************************************
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* A generic function to find the default circuit model with a given type
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* If not found, we give an error
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***********************************************************************/
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static
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size_t check_required_default_circuit_model(const CircuitLibrary& circuit_lib,
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const enum e_spice_model_type& circuit_model_type) {
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size_t num_err = 0;
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2019-08-19 21:43:35 -05:00
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if (CircuitModelId::INVALID() == circuit_lib.default_model(circuit_model_type)) {
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2019-08-13 14:25:23 -05:00
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vpr_printf(TIO_MESSAGE_ERROR,
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"A default circuit model for the type %s! Try to define it in your architecture file!\n",
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CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_model_type)]);
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exit(1);
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}
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return num_err;
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}
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/************************************************************************
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* A function to check the port map of FF circuit model
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***********************************************************************/
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size_t check_ff_circuit_model_ports(const CircuitLibrary& circuit_lib,
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const CircuitModelId& circuit_model) {
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size_t num_err = 0;
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/* Check the type of circuit model */
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2019-08-19 21:43:35 -05:00
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VTR_ASSERT(SPICE_MODEL_FF == circuit_lib.model_type(circuit_model));
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2019-08-13 14:25:23 -05:00
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/* Check if we have D, Set and Reset */
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num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model,
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SPICE_MODEL_PORT_INPUT,
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3, 1, false);
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/* Check if we have a clock */
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num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model,
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SPICE_MODEL_PORT_CLOCK,
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1, 1, false);
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/* Check if we have output */
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num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model,
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SPICE_MODEL_PORT_OUTPUT,
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1, 1, false);
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return num_err;
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}
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/************************************************************************
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2019-09-26 12:32:57 -05:00
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* A function to check the port map of CCFF circuit model
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2019-08-13 14:25:23 -05:00
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***********************************************************************/
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2019-09-26 12:32:57 -05:00
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size_t check_ccff_circuit_model_ports(const CircuitLibrary& circuit_lib,
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2019-08-13 14:25:23 -05:00
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const CircuitModelId& circuit_model) {
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size_t num_err = 0;
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/* Check the type of circuit model */
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2019-09-26 12:32:57 -05:00
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VTR_ASSERT(SPICE_MODEL_CCFF == circuit_lib.model_type(circuit_model));
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2019-08-13 14:25:23 -05:00
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/* Check if we have D, Set and Reset */
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num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model,
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SPICE_MODEL_PORT_INPUT,
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1, 1, false);
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/* Check if we have a clock */
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num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model,
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SPICE_MODEL_PORT_CLOCK,
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1, 1, true);
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/* Check if we have output */
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num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model,
|
|
|
|
SPICE_MODEL_PORT_OUTPUT,
|
|
|
|
2, 1, false);
|
|
|
|
|
|
|
|
return num_err;
|
|
|
|
}
|
|
|
|
|
|
|
|
/************************************************************************
|
|
|
|
* A function to check the port map of SRAM circuit model
|
|
|
|
***********************************************************************/
|
|
|
|
size_t check_sram_circuit_model_ports(const CircuitLibrary& circuit_lib,
|
|
|
|
const CircuitModelId& circuit_model,
|
|
|
|
const bool& check_blwl) {
|
|
|
|
size_t num_err = 0;
|
|
|
|
|
|
|
|
/* Check the type of circuit model */
|
2019-08-19 21:43:35 -05:00
|
|
|
VTR_ASSERT(SPICE_MODEL_SRAM == circuit_lib.model_type(circuit_model));
|
2019-08-13 14:25:23 -05:00
|
|
|
|
|
|
|
/* Check if we has 1 output with size 2 */
|
|
|
|
num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model,
|
|
|
|
SPICE_MODEL_PORT_OUTPUT,
|
|
|
|
1, 2, false);
|
|
|
|
/* basic check finished here */
|
|
|
|
if (false == check_blwl) {
|
|
|
|
return num_err;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* If bl and wl are required, check their existence */
|
|
|
|
num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model,
|
|
|
|
SPICE_MODEL_PORT_BL,
|
|
|
|
1, 1, false);
|
|
|
|
|
|
|
|
num_err += check_one_circuit_model_port_type_and_size_required(circuit_lib, circuit_model,
|
|
|
|
SPICE_MODEL_PORT_WL,
|
|
|
|
1, 1, false);
|
|
|
|
|
|
|
|
return num_err;
|
|
|
|
}
|
|
|
|
|
2019-08-23 00:48:46 -05:00
|
|
|
/* Check all the ports make sure, they satisfy the restriction */
|
|
|
|
static
|
|
|
|
size_t check_circuit_library_ports(const CircuitLibrary& circuit_lib) {
|
|
|
|
size_t num_err = 0;
|
|
|
|
|
|
|
|
/* Check global ports: make sure all the global ports are input ports */
|
|
|
|
for (const auto& port : circuit_lib.ports()) {
|
|
|
|
if ( (circuit_lib.port_is_global(port))
|
|
|
|
&& (!circuit_lib.is_input_port(port)) ) {
|
|
|
|
vpr_printf(TIO_MESSAGE_ERROR,
|
|
|
|
"Circuit port (type=%s) of model (name=%s) is defined as global but not an input port!\n",
|
|
|
|
CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(port))],
|
|
|
|
circuit_lib.model_name(port).c_str());
|
|
|
|
num_err++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Check set/reset/config_enable ports: make sure they are all global ports */
|
|
|
|
for (const auto& port : circuit_lib.ports()) {
|
|
|
|
if ( ( (circuit_lib.port_is_set(port))
|
|
|
|
|| (circuit_lib.port_is_reset(port))
|
|
|
|
|| (circuit_lib.port_is_config_enable(port)) )
|
|
|
|
&& (!circuit_lib.port_is_global(port)) ) {
|
|
|
|
vpr_printf(TIO_MESSAGE_ERROR,
|
|
|
|
"Circuit port (type=%s) of model (name=%s) is defined as a set/reset/config_enable port but it is not global!\n",
|
|
|
|
CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(port))],
|
|
|
|
circuit_lib.model_name(port).c_str());
|
|
|
|
num_err++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-09-11 18:04:43 -05:00
|
|
|
/* Check the tri-state map of ports, the length should match the port size! */
|
|
|
|
for (const auto& port : circuit_lib.ports()) {
|
|
|
|
if (circuit_lib.port_tri_state_map(port).empty()) {
|
|
|
|
continue; /* No tri-state map is found, go to the next */
|
|
|
|
}
|
|
|
|
if (circuit_lib.port_tri_state_map(port).length() == circuit_lib.port_size(port)) {
|
|
|
|
continue; /* Sizes match, go to the next */
|
|
|
|
}
|
|
|
|
/* We have a problem here, sizes do not match, leave a message and raise the error flag */
|
|
|
|
vpr_printf(TIO_MESSAGE_ERROR,
|
|
|
|
"Tri-state map (=%s) of circuit port (type=%s) of model (name=%s) does not match the port size (=%lu)!\n",
|
|
|
|
circuit_lib.port_tri_state_map(port).c_str(),
|
|
|
|
CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(port))],
|
|
|
|
circuit_lib.model_name(port).c_str(),
|
|
|
|
circuit_lib.port_size(port));
|
|
|
|
num_err++;
|
|
|
|
}
|
|
|
|
|
2019-08-23 00:48:46 -05:00
|
|
|
return num_err;
|
|
|
|
}
|
2019-08-13 14:25:23 -05:00
|
|
|
|
2019-08-12 17:45:33 -05:00
|
|
|
/************************************************************************
|
|
|
|
* Check points to make sure we have a valid circuit library
|
|
|
|
* Detailed checkpoints:
|
|
|
|
* 1. Circuit models have unique names
|
|
|
|
* 2. Circuit models have unique prefix
|
|
|
|
* 3. Check IOPADs have input and output ports
|
|
|
|
* 4. Check MUXes has been defined and has input and output ports
|
2019-09-26 12:32:57 -05:00
|
|
|
* 5. We must have at least one SRAM or CCFF
|
2019-08-13 14:25:23 -05:00
|
|
|
* 6. SRAM must have at least an input and an output ports
|
2019-09-26 12:32:57 -05:00
|
|
|
* 7. CCFF must have at least a clock, an input and an output ports
|
2019-08-13 14:25:23 -05:00
|
|
|
* 8. FF must have at least a clock, an input and an output ports
|
|
|
|
* 9. LUT must have at least an input, an output and a SRAM ports
|
|
|
|
* 10. We must have default circuit models for these types: MUX, channel wires and wires
|
2019-08-12 17:45:33 -05:00
|
|
|
***********************************************************************/
|
|
|
|
void check_circuit_library(const CircuitLibrary& circuit_lib) {
|
|
|
|
size_t num_err = 0;
|
|
|
|
|
|
|
|
vpr_printf(TIO_MESSAGE_INFO, "Checking circuit models...\n");
|
|
|
|
|
|
|
|
/* 1. Circuit models have unique names
|
|
|
|
* For each circuit model, we always make sure it does not share any name with any circuit model locating after it
|
|
|
|
*/
|
|
|
|
num_err += check_circuit_library_unique_names(circuit_lib);
|
|
|
|
|
|
|
|
/* 2. Circuit models have unique prefix
|
|
|
|
* For each circuit model, we always make sure it does not share any prefix with any circuit model locating after it
|
|
|
|
*/
|
|
|
|
num_err += check_circuit_library_unique_prefix(circuit_lib);
|
|
|
|
|
2019-08-23 00:48:46 -05:00
|
|
|
/* Check global ports */
|
|
|
|
num_err += check_circuit_library_ports(circuit_lib);
|
|
|
|
|
2019-08-12 17:45:33 -05:00
|
|
|
/* 3. Check io has been defined and has input and output ports
|
|
|
|
* [a] We must have an IOPAD!
|
|
|
|
* [b] For each IOPAD, we must have at least an input, an output, an INOUT and an SRAM port
|
|
|
|
*/
|
|
|
|
num_err += check_circuit_model_required(circuit_lib, SPICE_MODEL_IOPAD);
|
|
|
|
|
|
|
|
std::vector<enum e_spice_model_port_type> iopad_port_types_required;
|
|
|
|
iopad_port_types_required.push_back(SPICE_MODEL_PORT_INPUT);
|
|
|
|
iopad_port_types_required.push_back(SPICE_MODEL_PORT_OUTPUT);
|
|
|
|
iopad_port_types_required.push_back(SPICE_MODEL_PORT_INOUT);
|
|
|
|
iopad_port_types_required.push_back(SPICE_MODEL_PORT_SRAM);
|
|
|
|
|
|
|
|
num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_IOPAD, iopad_port_types_required);
|
|
|
|
|
|
|
|
/* 4. Check mux has been defined and has input and output ports
|
|
|
|
* [a] We must have a MUX!
|
|
|
|
* [b] For each MUX, we must have at least an input, an output, and an SRAM port
|
|
|
|
*/
|
|
|
|
num_err += check_circuit_model_required(circuit_lib, SPICE_MODEL_MUX);
|
|
|
|
|
|
|
|
std::vector<enum e_spice_model_port_type> mux_port_types_required;
|
|
|
|
mux_port_types_required.push_back(SPICE_MODEL_PORT_INPUT);
|
|
|
|
mux_port_types_required.push_back(SPICE_MODEL_PORT_OUTPUT);
|
|
|
|
mux_port_types_required.push_back(SPICE_MODEL_PORT_SRAM);
|
|
|
|
|
|
|
|
num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_MUX, mux_port_types_required);
|
|
|
|
|
2019-09-26 12:32:57 -05:00
|
|
|
/* 5. We must have at least one SRAM or CCFF */
|
2019-08-19 21:43:35 -05:00
|
|
|
if ( ( 0 == circuit_lib.models_by_type(SPICE_MODEL_SRAM).size())
|
2019-09-26 12:32:57 -05:00
|
|
|
&& ( 0 == circuit_lib.models_by_type(SPICE_MODEL_CCFF).size()) ) {
|
2019-08-12 17:45:33 -05:00
|
|
|
vpr_printf(TIO_MESSAGE_ERROR,
|
|
|
|
"At least one %s or %s circuit model is required!\n",
|
|
|
|
CIRCUIT_MODEL_TYPE_STRING[size_t(SPICE_MODEL_SRAM)],
|
2019-09-26 12:32:57 -05:00
|
|
|
CIRCUIT_MODEL_TYPE_STRING[size_t(SPICE_MODEL_CCFF)]);
|
2019-08-12 17:45:33 -05:00
|
|
|
/* Incremental the counter for errors */
|
|
|
|
num_err++;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* 6. SRAM must have at least an input and an output ports*/
|
|
|
|
std::vector<enum e_spice_model_port_type> sram_port_types_required;
|
|
|
|
sram_port_types_required.push_back(SPICE_MODEL_PORT_INPUT);
|
|
|
|
sram_port_types_required.push_back(SPICE_MODEL_PORT_OUTPUT);
|
|
|
|
|
|
|
|
num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_SRAM, sram_port_types_required);
|
|
|
|
|
2019-09-26 12:32:57 -05:00
|
|
|
/* 7. CCFF must have at least a clock, an input and an output ports*/
|
|
|
|
std::vector<enum e_spice_model_port_type> ccff_port_types_required;
|
|
|
|
ccff_port_types_required.push_back(SPICE_MODEL_PORT_CLOCK);
|
|
|
|
ccff_port_types_required.push_back(SPICE_MODEL_PORT_INPUT);
|
|
|
|
ccff_port_types_required.push_back(SPICE_MODEL_PORT_OUTPUT);
|
2019-08-12 17:45:33 -05:00
|
|
|
|
2019-09-26 12:32:57 -05:00
|
|
|
num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_CCFF, ccff_port_types_required);
|
2019-08-12 17:45:33 -05:00
|
|
|
|
2019-08-13 14:25:23 -05:00
|
|
|
/* 8. FF must have at least a clock, an input and an output ports*/
|
2019-08-12 17:45:33 -05:00
|
|
|
std::vector<enum e_spice_model_port_type> ff_port_types_required;
|
|
|
|
ff_port_types_required.push_back(SPICE_MODEL_PORT_CLOCK);
|
|
|
|
ff_port_types_required.push_back(SPICE_MODEL_PORT_INPUT);
|
|
|
|
ff_port_types_required.push_back(SPICE_MODEL_PORT_OUTPUT);
|
|
|
|
|
|
|
|
num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_FF, ff_port_types_required);
|
|
|
|
|
2019-08-13 14:25:23 -05:00
|
|
|
/* 9. LUT must have at least an input, an output and a SRAM ports*/
|
2019-08-12 17:45:33 -05:00
|
|
|
std::vector<enum e_spice_model_port_type> lut_port_types_required;
|
|
|
|
lut_port_types_required.push_back(SPICE_MODEL_PORT_SRAM);
|
|
|
|
lut_port_types_required.push_back(SPICE_MODEL_PORT_INPUT);
|
|
|
|
lut_port_types_required.push_back(SPICE_MODEL_PORT_OUTPUT);
|
|
|
|
|
|
|
|
num_err += check_circuit_model_port_required(circuit_lib, SPICE_MODEL_LUT, lut_port_types_required);
|
|
|
|
|
2019-08-13 14:25:23 -05:00
|
|
|
/* 10. We must have default circuit models for these types: MUX, channel wires and wires */
|
|
|
|
num_err += check_required_default_circuit_model(circuit_lib, SPICE_MODEL_MUX);
|
|
|
|
num_err += check_required_default_circuit_model(circuit_lib, SPICE_MODEL_CHAN_WIRE);
|
|
|
|
num_err += check_required_default_circuit_model(circuit_lib, SPICE_MODEL_WIRE);
|
|
|
|
|
2019-08-12 17:45:33 -05:00
|
|
|
/* If we have any errors, exit */
|
2019-08-13 15:19:40 -05:00
|
|
|
vpr_printf(TIO_MESSAGE_INFO,
|
2019-08-12 17:45:33 -05:00
|
|
|
"Finished checking circuit library with %d errors!\n",
|
|
|
|
num_err);
|
|
|
|
|
|
|
|
if (0 < num_err) {
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/************************************************************************
|
|
|
|
* End of file : check_circuit_library.cpp
|
|
|
|
***********************************************************************/
|
|
|
|
|